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intel? PXA270 processor electrical, mechanical, and thermal specification data sheet n high-performance processor: ? intel xscale? micr oarchitecture with intel? wireless mmx? technology ? 7 stage pipeline ? 32 kb instruction cache ? 32 kb data cache ? 2 kb ?mini? data cache ? extensive data buffering n 256 kbytes of internal sram for high speed code or data storage preserved during low-power states n high-speed baseband processor interface (mobile scalable link) n rich serial peripheral set: ? ac?97 audio port ?i 2 s audio port ? usb client controller ? usb host controller ? usb on-the-go controller ? three high-speed uarts (two with hardware flow control) ? fir and sir infrar ed communications port n hardware debug features ? ieee jtag interface with boundary scan n hardware performance-monitoring features with on-chip trace buffer n real-time clock n operating-system timers n lcd controller n universal subscriber identity module interface n low power: ? wireless intel speedstep? technology ? less than 500 mw typical internal dissipation ? supply voltage may be reduced to 0.85 v ? four low-power modes ? dynamic voltage and frequency management n high-performance memory controller: ? four banks of sdram: up to 104 mhz @ 2.5v, 3.0v, and 3.3v i/o interface ? six static chip selects ? support for pcmcia and compact flash ? companion chip interface n flexible clocking: ? cpu clock from 104 to 624 mhz ? flexible memory clock ratios ? frequency changes ? functional clock gating n additional peripherals for system connectivity: ? sd card / mmc controller (with spi mode support) ? memory stick card controller ? three ssp controllers ?two i 2 c controllers ? four pulse-width modulators (pwms) ? keypad interface with both direct and matrix keys support ? most peripheral pins double as gpios order number 280002-002
ii electrical, mechanical, and thermal specification information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property righ ts is granted by this document. except as provided in intel's terms and conditions of sale for such products, in tel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products includi ng liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining applications. intel may make changes to specifications and pr oduct descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instru ctions marked "reserved" or "undefined. inte l reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the PXA270 processor may contain design defe cts or errors known as errata which may caus e the product to deviate from published specificat ions. current characterized errata are available on request. this document and the software described in it are furnished under license and may only be used or copied in accordance with th e terms of the license. the information in this document is furnished for informa tional use only, is subject to change without notice, and sho uld not be construed as a commitment by intel corporation. intel corp oration assumes no responsibility or liability for any errors or inaccuracies that m ay appear in this document or any software that may be provided in association wit h this document. except as permi tted by such license, no part o f this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of intel corporation. contact your local intel sales office or your distributor to obt ain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are refer enced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. alertview, anypoint, appchoice, boardwatch, bunnypeople, cableport, celeron, chips, ct connect, ct media, dialogic, dm3, ethere xpress, etox, flashfile, i386, i486, i960, icomp, instantip, intel, intel logo, intel386, intel486, intel740, inteldx2, inteldx4, intel sx2, intel create & share, intel gigablade, intel inbusiness, intel inside, intel inside logo, intel netburst, intel netmerge, intel netstructure, intel p lay, intel play logo, intel singledriver, intel speedstep, intel strataflash, intel teamstation, intel xeon, intel xscale, iplink, itanium, landesk, lanrov er, mcs, mmx, mmx logo, optimizer logo, overdrive, paragon, pc dads, pc parents, pd charm, pentium, pentium ii xeon, pentium iii xeon, performance at your command, remoteexpress, shiva, smartdie, solutions960, sound ma rk, storageexpress, the computer inside., the journey inside, tokenexpress, trillium, voicebrick, vtune, and xircom are trademarks or registered trademarks of intel corporation or its subsi diaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? intel corporation, 2004
intel? PXA270 processor contents electrical, mechanical, and thermal specification iii contents 1 introduction .........................................................................................................1-1 1.1 about this document.................................................................................1-1 1.1.1 number representation .............. ..................................................1-1 1.1.2 typographical conventions ...........................................................1-1 1.1.3 applicable documents................. ..................................................1-2 2 functional overview ...........................................................................................2-1 3 package information ...........................................................................................3-1 3.1 package information ..................................................................................3-1 3.2 processor materials....................................................................................3-6 3.3 junction to case temperature thermal resistance .................................3-7 3.4 processor markings....................................................................................3-7 3.5 tray drawing ..............................................................................................3-8 4 pin listing and signal definitions .....................................................................4-1 4.1 ball map view.............................................................................................4-2 4.1.1 13x13 mm vf-bga ball map ........................................................4-2 4.1.2 23x23 mm pbga ball map............................................................4-6 4.2 pin usage ...................................................................................................4-9 4.3 signal types.............................................................................................4-27 4.4 memory controller reset and initializat ion...............................................4-28 4.5 power-supply pins ...................................................................................4-29 5 electrical specifications .....................................................................................5-1 5.1 absolute maximum ratings........................................................................5-1 5.2 operating conditions..................................................................................5-1 5.2.1 internal power domains .............. ..................................................5-6 5.3 power-consumption specifications............................................................5-6 5.4 dc specification .........................................................................................5-8 5.5 oscillator electrical specifications..............................................................5-9 5.5.1 32.768-khz oscillator specifications .............................................5-9 5.5.2 13.000-mhz oscillator specifications..........................................5-11 5.6 clk_pio and clk_tout specifications ................................................5-12 5.7 48 mhz output specifications ..................................................................5-13 6 ac timing specifications ...................................................................................6-1 6.1 ac test load specifications ......................................................................6-1 6.2 reset and power manager timing spec ifications......................................6-2 6.2.1 power-on timing specifications ...................................................6-2 6.2.2 hardware reset timing.................................................................6-4 6.2.3 watchdog reset timing ................................................................6-5 6.2.4 gpio reset timing .......................................................................6-5 6.2.5 sleep mode timing .......................................................................6-6 6.2.6 deep-sleep mode timing..............................................................6-7
intel? PXA270 processor contents iv electrical, mechanical, and thermal specification 6.2.7 standby-mode timing .................................................................6-10 6.2.8 idle-mode timing.........................................................................6-10 6.2.9 frequency-change timing..........................................................6-10 6.2.10 voltage-change timing...............................................................6-11 6.3 gpio timing specifications .....................................................................6-11 6.4 memory and expansion-card timing specifications................................6-12 6.4.1 internal sram read/write timing specifications .......................6-12 6.4.2 sdram parameters and timing diagrams.................................6-12 6.4.3 rom parameters and timing di agrams .....................................6-18 6.4.4 flash memory parameters and timing diagrams.......................6-23 6.4.5 sram parameters and timing dia grams ...................................6-33 6.4.6 variable-latency i/o paramete rs and timing diagrams.............6-36 6.4.7 expansion-card interface parame ters and timing diagrams.....6-40 6.5 lcd timing specifications .......................................................................6-43 6.6 ssp timing specificatio ns ............. ................ ................ ................ ..........6-44 6.7 jtag boundary scan timing specifications............................................6-45 glossary .............................................................................................................glossary-1 figures 2-1 intel? PXA270 processor block diagram, typical system................................2-2 3-1 13x13mm vf-bga intel? PXA270 proce ssor package, top view .....................3-1 3-2 13x13mm vf-bga intel? PXA270 proc essor package, bottom view ...............3-2 3-3 13x13mm vf-bga intel? PXA270 proce ssor package, side view ...................3-3 3-4 vf-bga product information decoder...... .........................................................3-3 3-5 23x23 mm pbga intel? PXA270 processor package (top view) ....................3-4 3-6 23x23 mm pbga intel? PXA270 processo r package (bottom view) ...............3-4 3-7 23x23 mm pbga intel? PXA270 processo r package (side view) ...................3-5 3-8 pbga product information decoder ..................................................................3-5 3-9 13x13mm vf-bga intel? PXA270 proc essor package, bottom view ...............3-6 3-10intel? PXA270 processor production markings, (laser mark on top side)......3-7 4-1 13x13 mm vf-bga ball map, top view (upp er left quarter) .............................4-2 4-2 13x13 mm vf-bga ball map, top view ( upper right quarter) ...........................4-3 4-3 13x13 mm vf-bga ball map, top view ( bottom left quarter) ...........................4-4 4-4 13x13 mm vf-bga ball map, top view (bottom right quarter) ........................4-5 4-5 23x23 mm pbga ball map, top view (upper left quarter) ..............................4-6 4-6 23x23 mm pbga ball map, top view (upper right quarter)............................4-7 4-7 23x23 mm pbga ball map, top view (lower left quarter) ..............................4-8 4-8 23x23 mm pbga ball map, top view (low er right quarter)............................4-9 6-1 ac test load .....................................................................................................6-2 6-2 power on reset timing .....................................................................................6-3 6-3 hardware reset timing .....................................................................................6-4 6-4 gpio reset timing ............................................................................................6-5 6-5 sleep mode timing ............................................................................................6-7 6-6 deep-sleep-mode timing ..................................................................................6-8 6-7 sdram timing ................................................................................................6-15 6-8 sdram 4-beat read/4-beat write, different banks timing............................6-16 6-9 sdram 4-beat write/4-beat write, same bank-same row timing ...............6-17 6-10 sdram fly-by dma timing.............................................................................6-18
intel? PXA270 processor contents electrical, mechanical, and thermal specification v 6-11 32-bit non-burst rom, sram, or flash read timing .....................................6-20 6-12 32-bit burst-of-eight rom or flash read timing ............................................6-21 6-13 eight-beat burst read fr om 16-bit burst-of-four ro m or flash timing..........6-22 6-14 16-bit rom/flash/sram read for 4/2/ 1 bytes timing ....................................6-23 6-15 synchronous flash burst-of-eight read timing ..............................................6-26 6-16 synchronous flash stacked burst-of-e ight read timing ................................6-27 6-17 first-access latency configuration ti ming......................................................6-28 6-18 synchronous flash burst read example. ........................................................6-30 6-19 32-bit flash write timing .................................................................................6-31 6-20 32-bit stacked flash write timing ...................................................................6-32 6-21 16-bit flash write timing .................................................................................6-33 6-22 32-bit sram write timing .................. .............................................................6-35 6-23 16-bit sram writ e for 4/2/1 byte(s) timing .....................................................6-36 6-24 32-bit vlio read timi ng .................................................................................6-38 6-25 32-bit vlio write timing..................... .............................................................6-39 6-26 expansion-card memory or i/o 16-bit access timing.....................................6-41 6-27 expansion-card memory or i/o 16-bit access to 8-bi t device timing ............6-42 6-28 lcd timing definitions........................ .............................................................6-43 6-29 ssp master mode timing definitions........... ................ ................. ............ .......6-44 6-30 ssp slave mode transmitting data to an external peri pheral ........... .............6-44 6-31 ssp slave mode receiving data from ex ternal peripheral ... ................ ..........6-45 6-32 jtag boundary-scan timing...........................................................................6-46 tables 1-1 supplemental documentatio n ............................................................................1-2 3-1 processor material proper ties ............................................................................3-7 4-1 pin usage summary ........................................................................................4-10 4-2 pin usage and mapping notes............... ..........................................................4-27 4-3 signal types.....................................................................................................4-28 4-4 memory controller pin reset values ..... ..........................................................4-28 4-5 discrete (13x13 vf-bga ) power supply pin summary...................................4-29 5-1 absolute maximum ratings................................................................................5-1 5-2 voltage, temperature, and frequency electrical specifications........................5-2 5-3 memory voltage and frequency electrical specifications .................................5-4 5-4 core voltage and frequency electrical specifications.......................................5-4 5-5 internally generated powe r domain descriptions .............................................5-6 5-6 core voltage specifications for lower power modes .......................................5-6 5-7 power-consumption specifications....................................................................5-7 5-8 standard input, ou tput, and i/o pin dc operating conditions ..........................5-8 5-9 typical 32.768-khz crystal requirements .........................................................5-9 5-10 typical external 32.768-khz oscilla tor requirements ....................................5-11 5-11 typical 13.000-mhz crystal requirement s......................................................5-11 5-12 typical external 13.000-mhz oscillato r requirements.......... ..........................5-12 5-13 clk_pio specifications ...................................................................................5-12 5-14 clk_tout specifications ..................... ..........................................................5-12 5-15 48 mhz output specific ations ..........................................................................5-13 6-1 standard input, ou tput, and i/o-pin ac operating conditions ..........................6-1 6-2 power-on timing specifications (oscc[cri] = 0) ............................................6-3 6-3 hardware reset timing specifications (oscc[cri] = 0) ..................................6-4 6-4 hardware reset timing specifications (oscc[cri] = 1) .................................6-5
intel? PXA270 processor contents vi electrical, mechanical, and thermal specification 6-5 gpio reset timing specifications .....................................................................6-6 6-6 sleep-mode timing specifications .....................................................................6-7 6-7 deep-sleep mode timing specifications .. .........................................................6-8 6-8 gpio pu/pd timing specifications for deep-sleep mode .................................6-9 6-9 standby-mode timing specifications ...............................................................6-10 6-10 idle-mode timing specifications ......................................................................6-10 6-11 frequency-change timing specifications .......................................................6-10 6-12voltage-change ti ming specification for a 1-byte command .........................6-11 6-13 gpio timing specifications .............................................................................6-11 6-14sram read/write ac specification .. ..............................................................6-12 6-15 sdram interface ac specifications ................................................................6-13 6-16 rom ac specification .....................................................................................6-18 6-17 synchronous flash read ac specifications....................................................6-24 6-18 flash memory ac specification .......................................................................6-30 6-19 sram write ac specification ..........................................................................6-34 6-20 vlio timing .....................................................................................................6-37 6-21expansion-card interface ac specific ations ...................................................6-40 6-22 lcd timing specifications ...............................................................................6-43 6-23ssp master mode timing specificati ons .........................................................6-44 6-24ssp slave mode transmitting data to external peripheral .............................6-45 6-25 ssp slave mode receiving data from external peripheral .............................6-45 6-26 boundary scan timing specifications..............................................................6-45
intel? PXA270 processor contents electrical, mechanical, and thermal specification vii revision history date revision description april 2004 -001 first public release of the emts june 2004 -002 added 23x23 mm 360-ball pbga package
intel? PXA270 processor contents viii electrical, mechanical, and thermal specification
electrical, mechanical, and thermal specification 1-1 introduction 1 the intel? PXA270 processor (PXA270 processor) provides industry-leading multimedia performance, low-power capabilities, rich periphe ral integration and second generation memory stacking. designed from the ground up for wireless cl ients, it incorporates the latest intel advances in mobile technology over its predecessor, the inte l? pxa255 processor. these same attributes and features also make the PXA270 processor ideal for embedded applications. the PXA270 processor redefines scalability by operating fr om 104 mhz up to 624 mhz, providing enough performance for the most demanding mobile applications. the PXA270 processor is the first intel processor to include intel? wireless mmx? technology, enabling high-performance, low-pow er multimedia acceleration with a general-purpose instruction set. intel? quick capture tec hnology provides a flexible and powerful camera interface for capturing digital images and video. while perfor mance is key in the PXA270 processor, power consumption is also a critical component. the new capabilities of wireless intel speedstep? technology set the standard for low-power consumption. the PXA270 processor is offered in two packages: 13x13 mm vfbga and 23x23 mm pbga. 1.1 about this document this document constitutes the electrical, mechan ical, and thermal specifi cations for the PXA270 processor. it contains a functional overview, m echanical data, package signal locations, targeted electrical specifications, and functi onal bus waveforms. for detailed functional descriptions other than parametric performance, refer to the intel? pxa27x processor family developers manual . 1.1.1 number representation all numbers in this document are base 10 unless designated otherwise. hexadecimal numbers have a prefix of 0x, and binary numbers have a prefix of 0b. for example, 107 is represented as 0x6b in hexadecimal and 0b110_1011 in binary. 1.1.2 typographical conventions all signal and register-bit names appear in u ppercase. active low items are prefixed with a lowercase ?n?. bits within a signal name ar e enclosed in angle brackets: external_address<31:0> ncs<1> bits within a register bit field are enclosed in square brackets: register_bitfield[3:0] register_bit[0]
1-2 electrical, mechanical, and thermal specification intel? PXA270 processor introduction single-bit items have either of two states: ? clear ? the item contains the value 0b0. to clear a bit, write 0b0 to it. ? set ? the item contains the value 0b1. to set a bit, write 0b1 to it. 1.1.3 applicable documents table 1-1 lists supplemental information sources fo r the PXA270 processor. contact an intel representative for the latest document revisions and ordering instructions. table 1-1. supplemental documentation document title intel? pxa27x processor family developers manual arm ? architecture versi on 5t specification (document number arm* ddi 0100d-10), and arm ? architecture reference manual (document number arm* ddi 0100b) intel ? xscale? core developer?s manual intel? wireless mmx? technology developer?s guide intel? pxa27x processor design guide intel? pxa27x processor power s upply requirements application note
electrical, mechanical, and thermal specification 2-1 functional overview 2 the intel? PXA270 processor is an integrat ed system-on-a-chip mi croprocessor for high performance, dynamic, low-power portable handhel d and hand-set devices as well as embedded platforms. it incorporates the intel xscale? technology which complies with the arm* version 5te instruction set (excluding floating-point instructions) and follows the arm* programmer?s model. the PXA270 processor also provides intel? wireless mmx? media enhancement technology, which supports integer instructions to accelerate audio and video processing. in addition, it incorporates wireless intel speedstep? technology, which provides sophisticated power management capabilities enabli ng excellent mips/mw performance. the PXA270 processor provi des a scalable, bi-directional data interface to a cellular baseband processor, supporting seven logical channels and other features. the operating-system (os) timer channels and synchronous serial ports (ssps) also accept an external network clock input so that they can be synchronized to the cellular networ k. the processor also provides a universal subscriber identity module* (usim) card interface. the PXA270 processor memory interface gives desi gners flexibility as it supports a variety of external memory types. the processor also provides four 64 kilobyte banks of on-chip sram, which can be used for program code or mul timedia data. each bank can be configured independently to retain its contents when the pr ocessor enters a low-power mode. an integrated lcd panel controller supports displays up to 800 by 600 pixels, permitting 1-, 2-, 4-, and 8-bit gray scale and 1-, 2-, 4-, 8-, 16-, 18-, and 24-bit colo r pixels. a 256-byte palette ram provides flexible color mapping. a set of serial devices and general-system re sources offers computational and connectivity capability for a variety of applications. figure 2-1 shows the block diagram for a typical PXA270 processor system.
2-2 electrical, mechanical, and thermal specification intel? PXA270 processor functional overview figure 2-1. intel? PXA270 processor block diagram, typical system general purpose i/o dma controller and bridge mhz osc xscale? micro- memory controller pcmcia & cf control variable control dynamic control static control memory memory latency i/o asic xcvr rom/ flash/ sram socket 0 socket 1 intel? wireless mmx? usb host system bus controller internal sram 13 power management clock control primary gpio peripheral bus address and data address and data bus ac97 rtc i 2 s os timers 4 x pwm interrupt usim 3 x ssp irda i 2 c full function uart usb client bb processor interface keypad interface bluetooth uart sdcard/mmc interface memory stick interface lcd lcd khz osc 32.768 controller architecture intel? jtag controller debug usb otg camera interface sdram general p ur pos e i /o dma controller and bridge mhz os c xscale? mi cro - memory controller pcmcia & cf control var ia ble control dynamic control static control memory memory latency i/o as ic xcvr sdram/ boot rom/ flash/ sram soc ket 0 soc ket 1 intel? wireless mmx? usb ho st sy stem bus controller in tern al sram 13 power management clock cont ro l p rimar y gp io per iphera l bus addr ess and data address and data b us ac 97 rt c i 2 s os timers 4 x pwm i nterru pt usim 3 x ssp irda i 2 c full function ua rt usb client bb processor interface k e yp ad interface bluet oot h* uart sdcard/mmc interface memory stick int erface lc d lcd khz osc 32 .76 8 controller architecture in tel? jtag controller debug rom usb otg camera interface ?
electrical, mechanical, and thermal specification 3-1 package information 3 this chapter provides the mechanical specifications for the PXA270 processor. the PXA270 processor is offered in two packag es. the 13- by 13-mm, 356-ball, 0.50-mm vf- bga molded matrix array package is shown in figure 3-1 , figure 3-2 , and figure 3-3 . the 23- by 23-mm, 360-ball, 1.0-mm pbga molded matrix array package is shown in figure 3-5 , figure 3-6 , and figure 3-7 . 3.1 package information figure 3-1. 13x13mm vf-bga intel? PXA270 processor package, top view a b c d e f g h j k l m n p r t u v w y aa ab ac ad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a1 corner
3-2 electrical, mechanical, and thermal specification intel? PXA270 processor package information note: figure 3-2 and figure 3-3 show all dimensions in millimeters (mm). figure 3-2. 13x13mm vf-bga intel? PXA270 processor package, bottom view 11.50 11.50 0.50 0.50 a b 0.15 m c a b 0.15 m c ?0.300.05 (356) 130.10 130.10
electrical, mechanical, and thermal specification 3-3 intel? PXA270 processor package information figure 3-4. vf-bga product information decoder figure 3-3. 13x13mm vf-bga intel? PXA270 processor package, side view 0.210.04 0.450.05 0.18 min. ? 0.30 max. 1.0 max. 0.10 c 0.12 c c seating plane 0.91 min. - intel xscale? family product family member 270=discrete product package type lv=leaded rc=lead-free commercial temperature rating speed 312 mhz 416 mhz 520 mhz 624 mhz stepping r c PXA270 c0c 4 16
3-4 electrical, mechanical, and thermal specification intel? PXA270 processor package information note: figure 3-5 , figure 3-6 and figure 3-7 show all dimensions in millimeters (mm). figure 3-5. 23x23 mm pbga intel ? PXA270 processor package (top view) a1 corner 14.70 0.25 figure 3-6. 23x23 mm pbga intel ? PXA270 processor package (bottom view) 1.00 1.00 1.00 17 16 15 14 13 12 1.00 u t r p n m l k j h g f corner pin #1 4 11 10 9 8 7 6 5 e d c b a 3 2 1 v w y aa ab 18 19 20 21 22
electrical, mechanical, and thermal specification 3-5 intel? PXA270 processor package information figure 3-7. 23x23 mm pbga intel ? PXA270 processor package (side view) 0.20 c c 0.15 // seating plane 3 figure 3-8. pbga product information decoder intel xscale? family product family member 270 = discrete product package type fw = leaded nh = lead-free temperature rating c = -25 to 85 c e = -40 to 85 c speed 312 mhz 416 mhz 520 mhz stepping f w PXA270 c 1 c 4 16
3-6 electrical, mechanical, and thermal specification intel? PXA270 processor package information 3.2 processor materials figure 3-9. 13x13mm vf-bga intel? PXA270 processor package, bottom view table 3-1 describes the basic material prop erties of the processor components.
electrical, mechanical, and thermal specification 3-7 intel? PXA270 processor package information 3.3 junction to case temperature thermal resistance 3.4 processor markings the diagram in this section details the processor?s top markings, which identify the PXA270 processor in the 356-ball vf-bga an d 360-ball pbga package. refer to figure 3-4 for product information. a pb-free (l ead-free) package is indicated by th e letter ?e? on the 3rd line of information (intel legal line). the ?e? appears after the date stamp. table 3-1. processor material properties component vf-bga material pbga material mold compound shinetsu kmc 2500 vat1 sumitomo g770le solder balls 63 sn/37 pb ? 63 sn/37 pb ? ? subsequent processor steppings may use pb-free (94.5 sn/5.0 ag/ 0.5 cu) balls . parameter vf-bga value and units pbga value and units theta jc 2 degrees c / watt 1.4 degrees c / watt figure 3-10. intel? PXA270 processor production markings, (laser mark on top side) g laser mark on top side of package product lot # intel legal i PXA270c0c416 fpo# m c ?03 taiwan pin 1 indicator coo g laser mark on top side of package product lot # intel legal i PXA270c0c416 fpo# m c ?03 taiwan pin 1 indicator coo
3-8 electrical, mechanical, and thermal specification intel? PXA270 processor package information 3.5 tray drawing for tray drawing information, refer to the intel developer website for the intel? wireless communications and computing package users guide .
electrical, mechanical, and thermal specification 4-1 pin listing and signal definitions 4 this chapter describes the signals and pins for the intel? PXA270 processor. for descriptions of all PXA270 processor signals, refer to the ?system architecture? chapter in the intel? pxa27x processor family developer?s manual . table 4-2 lists the mapping of signals to specific package pins. many of the package pins are multiplexed so that they can be configured for us e as a general purpose i/o signal or as one of two or three alternate functions using the gpio alternate-function se lect registers. some signals can be configured to appear on one of several different package pins.
4-2 electrical, mechanical, and thermal specification intel? PXA270 processor pin listing and si gnal definitions 4.1 ball map view note: in the following ball map figures the lowercase letter ?n?, which normally indicates negation, appears as uppercase ?n?. 4.1.1 13x13 mm vf-bga ball map figure 4-1 through figure 4-4 shows the ball map for the vf-bga PXA270 processor. figure 4-1. 13x13 mm vf-bga ball map, top view (upper left quarter) 123456789101112 a vss_core vss_core gpio<15> vcc_mem vcc_sram ma<1> vcc_core vcc_sram vcc_sram gpio<49> gpio<47> vcc_io b vss_core vss_core ncs<0> vcc_sram vss_core gpio<33> gpio<78> vcc_mem gpio<18> gpio<12> gpio<46> vcc_core c ma<18> ma<22> vcc_mem ma<24> vss_mem ma<0> gpio<80> gpio<79> rdnwr gpio<13> gpio<11> gpio<31> d ma<17> ma<21> vcc_core ma<23> vss_mem ma<25> vss_core vss_core vss_mem vss_core vss_io vss_core e ma<13> vcc_mem ma<19> ma<20> f vcc_mem ma<14> ma<16> vss_mem g ma<8> ma<11> ma<12> ma<15> h vcc_mem ma<9> ma<10> vss_mem j ma<3> ma<6> ma<7> vss_mem k md<15> ma<4> ma<5> ma<2> vss_core vss_core vss_core l md<14> md<31> vcc_mem vss_mem vss_core vss_core vss_core m vcc_mem md<30> md<29> md<13> vss_core vss_core vss_core
electrical, mechanical, and thermal specification 4-3 intel? PXA270 processor pin listing and si gnal definitions figure 4-2. 13x13 mm vf-bga ball map, top view (upper right quarter) 13 14 15 16 17 18 19 20 21 22 23 24 gpio<113> gpio<28> gpio<37> vcc_io gpio<24> gpio<16> gpio<92> gpio<32> gpio<34> gpio<118> vcc_usb vcc_usb a gpio<29> gpio<38> gpio<26> gpio<23> gpio<110> gpio<112> gpio<35> gpio<44> vcc_core usbc_p vcc_usb vcc_usb b gpio<30> gpio<36> gpio<27> gpio<17> gpio<111> gpio<41> gpio<45> usbc_n gpio<42> gpio<43> gpio<88> gpio<116> c gpio<22> gpio<40> vss_io gpio<25> gpio<109> vss_io gpio<39> gpio<117> vss_core gpio<89> usbh_n<1> gpio<114> d gpio<115> usbh_p<1> uio vcc_usim e vss_io gpio<90> gpio<91> vcc_core f vss_core gpio<59> gpio<60> gpio<58> g vss_io gpio<62> gpio<63> gpio<61> h vss_core gpio<64> vcc_core vcc_lcd j vss_core vss_core vss_core vss_core gpio<66> gpio<67> gpio<65> k vss_core vss_core vss_core gpio<68> gpio<71> gpio<69> vcc_core l vss_core vss_core vss_core vss_core gpio<73> vcc_core gpio<70> m
4-4 electrical, mechanical, and thermal specification intel? PXA270 processor pin listing and si gnal definitions figure 4-3. 13x13 mm vf-bga ball map, top view (bottom left quarter) n md<27> md<28> md<12> vss_mem vss_core vss_core vss_core p vcc_mem md<11> md<26> md<10> vss_core vss_core vss_core r md<24> vss_mem md<25> md<9> vss_core vss_core vss_core t md<23> vcc_core md<8> vss_mem u md<7> vcc_mem vss_core md<5> v md<21> md<22> md<6> vss_mem w md<20> vcc_mem vcc_core vss_core y md<19> md<4> md<3> vss_mem aa md<18> vcc_mem md<2> md<16> vss_mem nsdcas vss_core vss_mem vss_mem gpio<55> gpio<84> vss_core ab md<1> vss_mem md<17> md<0> nwe gpio<20> nsdcs<0> nsdcs<1> dqm<0> dqm<1> gpio<56> gpio<81> ac vcc_mem vcc_mem vss_mem sdclk<0> noe vcc_mem nsdras vcc_mem dqm<2> dqm<3> gpio<57> gpio<85> ad vcc_mem vcc_mem sdclk<2> vcc_core gpio<21> sdcke sdclk<1> vcc_mem gpio<82> gpio<83> vcc_core vcc_bb 123456789101112
electrical, mechanical, and thermal specification 4-5 intel? PXA270 processor pin listing and si gnal definitions figure 4-4. 13x13 mm vf-bga ball map, top view (bottom right quarter) vss_core vss_core vss_core vss_io gpio<86> gpio<87> gpio<72> n vss_core vss_core vss_core vss_core gpio<76> gpio<75> vcc_lcd p vss_core vss_core vss_core gpio<77> gpio<19> gpio<74> vcc_core r tms tck testclk gpio<14> t ntrst gpio<9> tdi vss_io u vss gpio<0> gpio<10> tdo v gpio<3> nvdd_faul t gpio<4> clk_req w nreset_o ut nreset pwr_en gpio<1> y vss_bb gpio<54> vss_core vss_io gpio<97> gpio<95> vss_io pwr_cap< 3> vss txtal_in txtal_out sys_en aa gpio<50> gpio<53> gpio<106> gpio<105> gpio<102> gpio<99> gpio<93> vcc_batt pwr_cap< 0> pwr_out boot_sel nbatt_fau lt ab gpio<48> gpio<52> gpio<107> gpio<103> gpio<101> gpio<100> gpio<96> vcc_pll pxtal_in pwr_cap< 2> vss vss ac gpio<51> gpio<108> gpio<104> vcc_core vcc_io gpio<98> gpio<94> vss_pll pxtal_out pwr_cap< 1> vss vss ad 13 14 15 16 17 18 19 20 21 22 23 24
4-6 electrical, mechanical, and thermal specification intel? PXA270 processor pin listing and si gnal definitions 4.1.2 23x23 mm pbga ball map figure 4-5. 23x23 mm pbga ball map, top view (upper left quarter) 1234567891011 a vss_mem vss_mem ma[25] gpio[15] gpio[79] gpio[13] gpio[12] gpio[11] gpio[46] gpio[113] gpio[29] b vss_mem vcc_mem vss_mem vcc_ram ma[1] vss_mem vcc_ram vcc_ram vss_mem vcc_io gpio[30] c ma[16] ma[17] vcc_mem ma[24] vcc_ram vcc_mem gpio[33] rdnwr vcc_mem gpio[47] gpio[31] d ma[14] ma[15] ma[19] ma[22] ma[0] ncs_0 gpio[80] gpio[78] gpio[18] gpio[49] vcc_core e ma[11] ma[12] ma[21] ma[23] vss_core vcc_core vss_core vcc_core vss_core f ma[9] vss_mem vcc_mem ma[20] vcc_core g ma[7] ma[8] ma[13] ma[18] vss_core h ma[4] vss_mem vcc_mem ma[10] vcc_core j ma[3] ma[2] ma[6] ma[5] vss_core vss_core vss_core vss_core k md[15] md[30] vcc_mem md[31] vss_core vss_core vss_core l md[14] vss_mem md[29] vcc_core vss_core vss_core vss_core
electrical, mechanical, and thermal specification 4-7 intel? PXA270 processor pin listing and si gnal definitions figure 4-6. 23x23 mm pbga ball map, top view (upper right quarter) 12 13 14 15 16 17 18 19 20 21 22 gpio[22] gpio[38] gpio[26] gpio[25] gpio[23] gpio[111] gpio[92] gpio[41] gpio[44] vcc_usb vcc_usb a vss_io gpio[36] gpio[24] vss_io gpio[112] gpio[39] vss_io gpio[34] gpio[118] gpio[43] vcc_usb b gpio[40] gpio[27] gpio[16] gpio[110] gpio[32] gpio[45] gpio[117] nc nc gpio[89] gpio[88] c gpio[28] gpio[37] vcc_io gpio[17] gpio[109] gpio[35] usbc_p vcc_usb gpio[42] vss_io usbh_n[1] d vss_core vcc_core vss_core vcc_core vss_core usbc_n gpio[116] gpio[115] usbh_p[1] e vcc_core gpio[114] uio vcc_usim gpio[61] f vss_core gpio[91] gpio[58] gpio[60] gpio[62] g vcc_core gpio[90] gpio[59] vss_io gpio[64] h vss_core vss_core vss_core vss_core gpio[66] gpio[63] vcc_lcd gpio[69] j vss_core vss_core vss_core gpio[67] gpio[65] gpio[68] gpio[70] k vss_core vss_core vss_core vcc_core gpio[71] gpio[72] gpio[73] l
4-8 electrical, mechanical, and thermal specification intel? PXA270 processor pin listing and si gnal definitions figure 4-7. 23x23 mm pbga ball map, top view (lower left quarter) m md[13] md[11] vcc_mem md[12] vss_core vss_core vss_core n md[28] md[26] md[24] md[25] vss_core vss_core vss_core p md[27] vss_mem vcc_mem md[8] vss_core vss_core vss_core vss_core r md[10] md[23] md[21] md[7] vcc_core t md[9] vss_mem vcc_mem md[5] vss_core u md[22] md[6] md[4] md[2] vcc_core v md[20] vss_mem vcc_mem md[16] vss_core vcc_core vss_core vcc_core vss_core w md[19] md[18] md[1] md[0] gpio[20] nsdras sdcke dqm[0] gpio[55] gpio[81] vcc_core y md[3] md[17] vcc_mem nsdcas vcc_mem gpio[21] vcc_mem nsdcs[1] vcc_mem gpio[84] gpio[48] aa vss_mem vcc_mem nwe noe nsdcs[0] vss_mem dqm[1] gpio[82] vss_mem gpio[85] vcc_bb ab vss_mem vss_mem sdclk[0] sdclk[2] sdclk[1] dqm[2] dqm[3] gpio[56] gpio[57] gpio[83] vss_bb 1234567891011
electrical, mechanical, and thermal specification 4-9 intel? PXA270 processor pin listing and si gnal definitions 4.2 pin usage the pin usage summary shown in table 4-1 does not include the 36 cen ter balls identified as k10 through r15 (vf-bga) or j9 through p14 (pbga) , all of which function as vss_core (see the recommendations for connecting the 36 center balls in the intel? pxa27x processor family design guide ). each signal?s alternate function inputs are shown in the upper s ection of each signal row and the outputs are shown in the lower s ection of each signal row. for ex ample, gpio<48> has a primary input function of cif_dd<5> and a secondary output function of npoe. figure 4-8. 23x23 mm pbga ball map, top view (lower right quarter) vss_core vss_core vss_core vcc_lcd gpio[86] vss_io gpio[87] m vss_core vss_core vss_core vss_io gpio[75] gpio[76] gpio[74] n vss_core vss_core vss_core vss_core gpio[19] gpio[14] gpio[77] testclk p vcc_core tck tms tdo tdi r vss_core gpio[4] ntrst clk_req gpio[9] t vcc_core nbatt_fau lt gpio[0] gpio[1] gpio[10] u vss_core vcc_core vss_core vcc_core vss_core boot_sel nvdd_faul t sys_en gpio[3] v gpio[50] gpio[106] gpio[104] vcc_io gpio[96] pwr_cap [3] vss pwr_out nreset nreset_o ut pwr_en w gpio[52] gpio[105] gpio[102] gpio[97] gpio[93] vcc_batt pwr_cap [2] pwr_cap [0] vss txtal_in txtal_out y gpio[53] gpio[108] vss_io gpio[100] gpio[98] gpio[94] vss_io vss_pll pxtal_out pwr_cap [1] vss aa gpio[51] gpio[54] gpio[107] gpio[103] gpio[101] gpio[99] gpio[95] vcc_pll pxtal_in vss vss ab 12 13 14 15 16 17 18 19 20 21 22
4-10 electrical, mechanical, and thermal specification intel? PXA270 processor pin listing and si gnal definitions table 4-1. pin usage summary (sheet 1 of 17) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state vcc_mem d6 a3 ma<25> ocz ma<25> ma<25> ? ? refer to table 4-4 c4 c4 ma<24> ocz ma<24> ma<24> ? ? refer to table 4-4 d4 e4 ma<23> ocz ma<23> ma<23> ? ? refer to table 4-4 c2 d4 ma<22> ocz ma<22> ma<22> ? ? refer to table 4-4 d2 e3 ma<21> ocz ma<21> ma<21> ? ? refer to table 4-4 e4 f4 ma<20> ocz ma<20> ma<20> ? ? refer to table 4-4 e3 d3 ma<19> ocz ma<19> ma<19> ? ? refer to table 4-4 c1 g4 ma<18> ocz ma<18> ma<18> ? ? refer to table 4-4 d1 c2 ma<17> ocz ma<17> ma<17> ? ? refer to table 4-4 f3 c1 ma<16> ocz ma<16> ma<16> ? ? refer to table 4-4 g4 d2 ma<15> ocz ma<15> ma<15> ? ? refer to table 4-4 f2 d1 ma<14> ocz ma<14> ma<14> ? ? refer to table 4-4 e1 g3 ma<13> ocz ma<13> ma<13> ? ? refer to table 4-4 g3 e2 ma<12> ocz ma<12> ma<12> ? ? refer to table 4-4 g2 e1 ma<11> ocz ma<11> ma<11> ? ? refer to table 4-4 h3 h4 ma<10> ocz ma<10> ma<10> ? ? refer to table 4-4 h2 f1 ma<9> ocz ma<9> ma<9> ? ? refer to table 4-4 g1 g2 ma<8> ocz ma<8> ma<8> ? ? refer to table 4-4 j3 g1 ma<7> ocz ma<7> ma<7> ? ? refer to table 4-4 j2 j3 ma<6> ocz ma<6> ma<6> ? ? refer to table 4-4 k3 j4 ma<5> ocz ma<5> ma<5> ? ? refer to table 4-4 k2 h1 ma<4> ocz ma<4> ma<4> ? ? refer to table 4-4 j1 j1 ma<3> ocz ma<3> ma<3> ? ? refer to table 4-4 k4 j2 ma<2> ocz ma<2> ma<2> ? ? refer to table 4-4 a6 b5 ma<1> ocz ma<1> ma<1> ? ? refer to table 4-4 c6 d5 ma<0> ocz ma<0> ma<0> ? ? refer to table 4-4 l2 k4 md<31> icoc z md<31> md<31> ? ? refer to table 4-4 m2 k2 md<30> icoc z md<30> md<30> ? ? refer to table 4-4 m3 l3 md<29> icoc z md<29> md<29> ? ? refer to table 4-4 n2 n1 md<28> icoc z md<28> md<28> ? ? refer to table 4-4 note: refer to table 4-2 for numbered notes on reset and sleep states.
electrical, mechanical, and thermal specification 4-11 intel? PXA270 processor pin listing and si gnal definitions n1 p1 md<27> icoc z md<27> md<27> ? ? refer to table 4-4 p3 n2 md<26> icoc z md<26> md<26> ? ? refer to table 4-4 r3 n4 md<25> icoc z md<25> md<25> ? ? refer to table 4-4 r1 n3 md<24> icoc z md<24> md<24> ? ? refer to table 4-4 t1 r2 md<23> icoc z md<23> md<23> ? ? refer to table 4-4 v2 u1 md<22> icoc z md<22> md<22> ? ? refer to table 4-4 v1 r3 md<21> icoc z md<21> md<21> ? ? refer to table 4-4 w1 v1 md<20> icoc z md<20> md<20> ? ? refer to table 4-4 y1 w1 md<19> icoc z md<19> md<19> ? ? refer to table 4-4 aa1 w2 md<18> icoc z md<18> md<18> ? ? refer to table 4-4 ab3 y2 md<17> icoc z md<17> md<17> ? ? refer to table 4-4 aa4 v4 md<16> icoc z md<16> md<16> ? ? refer to table 4-4 k1 k1 md<15> icoc z md<15> md<15> ? ? refer to table 4-4 l1 l1 md<14> icoc z md<14> md<14> ? ? refer to table 4-4 m4 m1 md<13> icoc z md<13> md<13> ? ? refer to table 4-4 n3 m4 md<12> icoc z md<12> md<12> ? ? refer to table 4-4 p2 m2 md<11> icoc z md<11> md<11> ? ? refer to table 4-4 p4 r1 md<10> icoc z md<10> md<10> ? ? refer to table 4-4 r4 t1 md<9> icoc z md<9> md<9> ? ? refer to table 4-4 t3 p4 md<8> icoc z md<8> md<8> ? ? refer to table 4-4 u1 r4 md<7> icoc z md<7> md<7> ? ? refer to table 4-4 v3 u2 md<6> icoc z md<6> md<6> ? ? refer to table 4-4 table 4-1. pin usage summary (sheet 2 of 17) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4-2 for numbered notes on reset and sleep states.
4-12 electrical, mechanical, and thermal specification intel? PXA270 processor pin listing and si gnal definitions u4 t4 md<5> icoc z md<5> md<5> ? ? refer to table 4-4 y2 u3 md<4> icoc z md<4> md<4> ? ? refer to table 4-4 y3 y1 md<3> icoc z md<3> md<3> ? ? refer to table 4-4 aa3 u4 md<2> icoc z md<2> md<2> ? ? refer to table 4-4 ab1 w3 md<1> icoc z md<1> md<1> ? ? refer to table 4-4 ab4 w4 md<0> icoc z md<0> md<0> ? ? refer to table 4-4 ac5 aa4 noe ocz noe noe ? ? refer to table 4-4 ab5 aa3 nwe ocz nwe nwe ? ? refer to table 4-4 ac7 w6 nsdras ocz nsdras nsdras ? ? refer to table 4-4 aa6 y4 nsdcas ocz nsdcas nsdcas ? ? refer to table 4-4 ab9 w8 dqm<0> ocz dqm<0> dqm<0> ? ? refer to table 4-4 ab10 aa7 dqm<1> ocz dqm<1> dqm<1> ? ? refer to table 4-4 ac9 ab6 dqm<2> ocz dqm<2> dqm<2> ? ? refer to table 4-4 ac10 ab7 dqm<3> ocz dqm<3> dqm<3> ? ? refer to table 4-4 ab7 aa5 nsdcs<0 > ocz nsdcs<0> nsdcs<0> ? ? refer to table 4-4 ab8 y8 nsdcs<1 > oc nsdcs<1> nsdcs<1> ? ? refer to table 4-4 ad6 w7 sdcke oc sdcke sdcke ? ? refer to table 4-4 ac4 ab3 sdclk<0 > oc sdclk<0> sdclk<0> ? ? refer to table 4-4 ad7 ab5 sdclk<1 > ocz sdclk<1> sdclk<1> ? ? refer to table 4-4 ad3 ab4 sdclk<2 > oc sdclk<2> sdclk<2> ? ? refer to table 4-4 c9 c8 rdnwr ocz rdnwr rdnwr ? ? refer to table 4-4 b3 d6 ncs<0> ocz ncs<0> ncs<0> ? ? refer to table 4-4 a3 a4 gpio<15> icoc z gpio<15> ??? pu-1 note[1] note[4] npce<1> ncs<1> refer to table 4-4 ? b9 d9 gpio<18> icoc z gpio<18> rdy ? ? pd-0 note[1] note [3] ??? table 4-1. pin usage summary (sheet 3 of 17) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4-2 for numbered notes on reset and sleep states.
electrical, mechanical, and thermal specification 4-13 intel? PXA270 processor pin listing and si gnal definitions ab6 w5 gpio<20> icoc z gpio<20> dreq<0> mbreq ? pu-1 note[1] note[3] nsdcs<2> refer to table 4-4 ?? ad5 y6 gpio<21> icoc z gpio<21> ??? pu-1 note[1] note[3] nsdcs<3> refer to table 4-4 dval<0> mbgnt b6 c7 gpio<33> icoc z gpio<33> ffrxd 19 ffdsr 19 ? pu-1 note[1] note [4] dval<1> ncs<5> refer to table 4-4 mbgnt a10 d10 gpio<49> icoc z gpio<49> ??? pu-1 note[1] note [5] ? npwe refer to table 4-4 ? b7 d8 gpio<78> icoc z gpio<78> ??? pu-1 note[1] note[4] npce<2> ncs<2> refer to table 4-4 ? c8 a5 gpio<79> icoc z gpio<79> ??? pu-1 note[1] note[4] psktsel ncs<3> refer to table 4-4 pwm_out <2> c7 d7 gpio<80> icoc z gpio<80> dreq<1> mbreq ? pu-1 note[1] note[4] ? ncs<4> refer to table 4-4 pwm_out <3> vcc_bb ac13 y11 gpio<48> icoc z gpio<48> cif_dd<5> ? ? pu-1 note[1] note [5] bb_ob_dat<1 > npoe refer to table 4-4 ? ab13 w12 gpio<50> icoc z gpio<50> cif_dd<3> ? sspsclk<2 > pu-1 note[1] note [5] bb_ob_dat<2 > npioir refer to table 4-4 sspsclk<2 > ad13 ab12 gpio<51> icoc z gpio<51> cif_dd<2> ? ? pu-1 note[1] note [5] bb_ob_dat<3 > npioiw refer to table 4-4 ? table 4-1. pin usage summary (sheet 4 of 17) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4-2 for numbered notes on reset and sleep states.
4-14 electrical, mechanical, and thermal specification intel? PXA270 processor pin listing and si gnal definitions ac14 y12 gpio<52> icoc z gpio<52> cif_dd<4> sspsclk<3> ? pd-0 note[1] note [3] bb_ob_clk sspsclk<3> ? ab14 aa12 gpio<53> icoc z gpio<53> ffrxd usb_p2_3 ? pd-0 note[1] note [3] bb_ob_stb cif_mclk sspsyscl k aa14 ab13 gpio<54> icoc z gpio<54> ? bb_ob_wait cif_pclk pd-0 note[1] note [3] npce<2> ? aa10 w9 gpio<55> icoc z gpio<55> cif_dd<1> bb_ib_dat<1> ? pu-1 note[1] note [5] ?npreg ? ab11 ab8 gpio<56> icoc z gpio<56> npwait bb_ib_dat<2> ? pu-1 note[1] note [5] usb_p3_4 ? ? ac11 ab9 gpio<57> icoc z gpio<57> niois16 bb_ib_dat<3> ? pu-1 note[1] note [5] ? ? ssptxd ab12 w10 gpio<81> icoc z gpio<81> ? cif_dd<0> ? pu-1 note[1] note [3] ssptxd3 bb_ob_dat<0 > ? ad9 aa8 gpio<82> icoc z gpio<82> ssprxd3 bb_ib_dat<0> cif_dd<5> pu-1 note[1] note [3] ??ffdtr ad10 ab10 gpio<83> icoc z gpio<83> sspsfrm3 bb_ib_clk cif_dd<4> pd-0 note[1] note [3] sspsfrm3 fftxd ffrts aa11 y10 gpio<84> icoc z gpio<84> sspsclk3 bb_ib_stb cif_fv pd-0 note[1] note [3] sspsclk3 ? cif_fv ac12 aa10 gpio<85> icoc z gpio<85> ffrxd dreq<2> cif_lv pd-0 note[1] note [3] npce<1> bb_ib_wait cif_lv vcc_lcd t24 p20 gpio<14> icoc z gpio<14> l_vsync sspsfrm2 ? pd-0 note[1] note [3] ? sspsfrm2 uclk r22 p19 gpio<19> icoc z gpio<19> sspsclk2 ? ffrxd pd-0 note[1] note [3] sspsclk2 l_cs nurst g24 g20 gpio<58> icoc z gpio<58> ? ldd<0> ? pd-0 note[1] note [3] ? ldd<0> ? g22 h20 gpio<59> icoc z gpio<59> ? ldd<1> ? pd-0 note[1] note [3] ? ldd<1> ? g23 g21 gpio<60> icoc z gpio<60> ? ldd<2> ? pd-0 note[1] note [3] ? ldd<2> ? table 4-1. pin usage summary (sheet 5 of 17) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4-2 for numbered notes on reset and sleep states.
electrical, mechanical, and thermal specification 4-15 intel? PXA270 processor pin listing and si gnal definitions h24 f22 gpio<61> icoc z gpio<61> ? ldd<3> ? pd-0 note[1] note [3] ? ldd<3> ? h22 g22 gpio<62> icoc z gpio<62> ? ldd<4> ? pd-0 note[1] note [3] ? ldd<4> ? h23 j20 gpio<63> icoc z gpio<63> ? ldd<5> ? pd-0 note[1] note [3] ? ldd<5> ? j22 h22 gpio<64> icoc z gpio<64> ? ldd<6> ? pd-0 note[1] note [3] ? ldd<6> ? k24 k20 gpio<65> icoc z gpio<65> ? ldd<7> ? pd-0 note[1] note [3] ? ldd<7> ? k22 j19 gpio<66> icoc z gpio<66> ? ldd<8> ? pd-0 note[1] note [3] ? ldd<8> ? k23 k19 gpio<67> icoc z gpio<67> ? ldd<9> ? pd-0 note[1] note [3] ? ldd<9> ? l21 k21 gpio<68> icoc z gpio<68> ? ldd<10> ? pd-0 note[1] note [3] ? ldd<10> ? l23 j22 gpio<69> icoc z gpio<69> ?ldd<11>? pd-0 note[1] note [3] ?ldd<11>? m24 k22 gpio<70> icoc z gpio<70> ? ldd<12> ? pd-0 note[1] note [3] ? ldd<12> ? l22 l20 gpio<71> icoc z gpio<71> ? ldd<13> ? pd-0 note[1] note [3] ? ldd<13> ? n24 l21 gpio<72> icoc z gpio<72> ? ldd<14> ? pd-0 note[1] note [3] ? ldd<14> ? m22 l22 gpio<73> icoc z gpio<73> ? ldd<15> ? pd-0 note[1] note [3] ? ldd<15> ? r23 n22 gpio<74> icoc z gpio<74> ??? pd-0 note[1] note [3] ? l_fclk_rd ? p23 n20 gpio<75> icoc z gpio<75> ??? pd-0 note[1] note [3] ? l_lclk _a0 ? p22 n21 gpio<76> icoc z gpio<76> ??? pd-0 note[1] note [3] ?l_pclk_wr? r21 p21 gpio<77> icoc z gpio<77> ??? pd-0 note[1] note [3] ?l_bias? table 4-1. pin usage summary (sheet 6 of 17) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4-2 for numbered notes on reset and sleep states.
4-16 electrical, mechanical, and thermal specification intel? PXA270 processor pin listing and si gnal definitions n22 m20 gpio<86> icoc z gpio<86> ssprxd2 ldd<16> usb_p3_5 pd-0 note[1] note [3] npce<1> ldd<16> ? n23 m22 gpio<87> icoc z gpio<87> npce<2> ldd<17> usb_p3_1 pd-0 note[1] note [3] ssptxd2 ldd<17> sspsfrm2 vcc_io c11 a8 gpio<11> icoc z gpio<11> ext_sync<0> ssprxd2 usb_p3_1 pd-0 note[1] note [3], note[11 chout<0> pwm_out2 48_mhz b10 a7 gpio<12> icoc z gpio<12> ext_sync<1> cif_dd<7> ? pd-0 note[1] note [3], note[11 chout<1> pwm_out3 48_mhz c10 a6 gpio<13> icoc z gpio<13> clk_ext kp_dkin<7> kp_mkin< 7> pd-0 note[1] note [3], note[11] ssptxd2 ? ? a18 c14 gpio<16> icoc z gpio<16> kp_mkin<5> ? ? pd-0 note[1] note [3] ? pwm_out<0> fftxd c16 d15 gpio<17> icoc z gpio<17> kp_mkin<6> cif_dd<6> ? pd-0 note[1] note [3] ? pwm_out<1> ? d13 a12 gpio<22> icoc z gpio<22> sspextclk2 sspsclken2 sspsclk2 pd-0 note[1] note [3] kp_mkout<7> sspsysclk2 sspsclk2 b16 a16 gpio<23> icoc z gpio<23> ? sspsclk ? pd-0 note[1] note [3] cif_mclk sspsclk ? a17 b14 gpio<24> icoc z gpio<24> cif_fv sspsfrm ? pd-0 note[1] note [3] cif_fv sspsfrm ? d16 a15 gpio<25> icoc z gpio<25> cif_lv ? ? pd-0 note[1] note [3] cif_lv ssptxd ? b15 a14 gpio<26> icoc z gpio<26> ssprxd cif_pclk ffcts pd-0 note[1] note [3] ??? c15 c13 gpio<27> icoc z gpio<27> sspextclk sspsclken cif_dd<0> pd-0 note[1] note [3] sspsysclk ? ffrts a14 d12 gpio<28> icoc z gpio<28> ac97_bitclk i2s_bitclk sspsfrm pd-0 note[1] note [3] i2s_bitclk ? sspsfrm b13 a11 gpio<29> icoc z gpio<29> ac97_sdata_i n_0 i2s_sdata_in sspsclk pd-0 note[1] note [3] ssprxd2 ? sspsclk table 4-1. pin usage summary (sheet 7 of 17) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4-2 for numbered notes on reset and sleep states.
electrical, mechanical, and thermal specification 4-17 intel? PXA270 processor pin listing and si gnal definitions c13 b11 gpio<30> icoc z gpio<30> ??? pd-0 note[1] note [3] i2s_sdata_ou t ac97_sdata_ out usb_p3_2 c12 c11 gpio<31> icoc z gpio<31> ??? pd-0 note[1] note [3] i2s_sync ac97_sync usb_p3_6 a20 c16 gpio<32> icoc z gpio<32> ??? pd-0 note[1] note [3] mssclk mmclk ? a21 b19 gpio<34> icoc z gpio<34> ffrxd kp_mkin<3> sspsclk3 pd-0 note[1] note [3] usb_p2_2 ? sspsclk3 b19 d17 gpio<35> icoc z gpio<35> ffcts usb_p2_1 sspsfrm3 pd-0 note[1] note [3] ? kp_mkout<6 > ssptxd3 c14 b13 gpio<36> icoc z gpio<36> ffdcd sspsclk2 kp_mkin< 7> pd-0 note[1] note [3] usb_p2_4 sspsclk2 ? a15 d13 gpio<37> icoc z gpio<37> ffdsr sspsfrm2 kp_mkin< 3> pd-0 note[1] note [3] usb_p2_8 sspsfrm2 fftxd b14 a13 gpio<38> icoc z gpio<38> ffri kp_mkin<4> usb_p2_3 pd-0 note[1] note [3] ssptxd3 ssptxd2 pwm_out <1> d19 b17 gpio<39> icoc z gpio<39> kp_mkin<4> ? sspsfrm3 pd-0 note[1] note [3] usb_p2_6 fftxd sspsfrm3 d14 c12 gpio<40> icoc z gpio<40> ssprxd2 ? usb_p2_5 pd-0 note[1] note [3] kp_mkout<6> ffdtr sspsclk3 c18 a19 gpio<41> icoc z gpio<41> ffrxd usb_p2_7 ssprxd3 pd-0 note[1] note [3] kp_mkout<7> ffrts ? c21 d20 gpio<42> icoc z gpio<42> btrxd icp_rxd ? pd-0 note[1] note [3] ??cif_mclk c22 b21 gpio<43> icoc z gpio<43> ? ? cif_fv pd-0 note[1] note [3] icp_txd bttxd cif_fv b20 a20 gpio<44> icoc z gpio<44> btcts ? cif_lv pd-0 note[1] note [3] ??cif_lv c19 c17 gpio<45> icoc z gpio<45> ? ? cif_pclk pd-0 note[1] note [3] ac97_sysclk btrts sspsyscl k3 b11 a9 gpio<46> icoc z gpio<46> icp_rxd std_rxd ? pd-0 note[1] note [3] ?pwm_out<2>? table 4-1. pin usage summary (sheet 8 of 17) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4-2 for numbered notes on reset and sleep states.
4-18 electrical, mechanical, and thermal specification intel? PXA270 processor pin listing and si gnal definitions a11 c10 gpio<47> icoc z gpio<47> cif_dd<0> ? ? pd-0 note[1] note [3] std_txd icp_txd pwm_out <3> c23 c22 gpio<88> icoc z gpio<88> usbhpwr<1> ssprxd2 sspsfrm2 pd-0 note[1] note [3] ? ? sspsfrm2 d22 c21 gpio<89> icoc z gpio<89> ssprxd3 ? ffri pd-0 note[1] note [3] ac97_sysclk usbhpen<1> ssptxd2 a19 a18 gpio<92> icoc z gpio<92> mmdat<0> ? ? pd-0 note[1] note [3] mmdat<0> msbs ? ab19 y16 gpio<93> icoc z gpio<93> kp_dkin<0> cif_dd<6> ? pd-0 note[1] note [3] ac97_sdata_ out ?? ad19 aa17 gpio<94> icoc z gpio<94> kp_dkin<1> cif_dd<5> ? pd-0 note[1] note [3] ac97_sync ? ? aa18 ab18 gpio<95> icoc z gpio<95> kp_dkin<2> cif_dd<4> kp_mkin< 6> pd-0 note[1] note [3] ac97_reset_n ? ? ac19 w16 gpio<96> icoc z gpio<96> kp_dkin<3> mbreq ffrxd pd-0 note[1] note [3] dval<1> kp_mkout <6> aa17 y15 gpio<97> icoc z gpio<97> kp_dkin<4> dreq<1> kp_mkin< 3> pd-0 note[1] note [3] ?mbgnt? ad18 aa16 gpio<98> icoc z gpio<98> kp_dkin<5> cif_dd<0> kp_mkin< 4> pd-0 note [1] note [3] ac97_sysclk ? ffrts ab18 ab17 gpio<99> icoc z gpio<99> kp_dkin<6> ac97_sdata_i n_1 kp_mkin< 5> pd-0 note [1] note [3] ? ? fftxd ac18 aa15 gpio<100 > icoc z gpio<100> kp_mkin<0> dreq<2> ffcts pd-0 note[1] note [3] ??? ac17 ab16 gpio<101 > icoc z gpio<101> kp_mkin<1> ? ? pd-0 note[1] note [3] ??? ab17 y14 gpio<102 > icoc z gpio<102> kp_mkin<2> ? ffrxd pd-0 note[1] note [3] npce<1> ? ? ac16 ab15 gpio<103 > icoc z gpio<103> cif_dd<3> ? ? pd-0 note[1] note [3] ? kp_mkout<0 > ? table 4-1. pin usage summary (sheet 9 of 17) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4-2 for numbered notes on reset and sleep states.
electrical, mechanical, and thermal specification 4-19 intel? PXA270 processor pin listing and si gnal definitions ad15 w14 gpio<104 > icoc z gpio<104> cif_dd<2> ? ? pd-0 note[1] note [3] psktsel kp_mkout<1 > ? ab16 y13 gpio<105 > icoc z gpio<105> cif_dd<1> ? ? pd-0 note[1] note [3] npce<2> kp_mkout<2 > ? ab15 w13 gpio<106 > icoc z gpio<106> cif_dd<9> ? ? pd-0 note[1] note [3] ? kp_mkout<3 > ? ac15 ab14 gpio<107 > icoc z gpio<107> cif_dd<8> ? ? pd-0 note[1] note [3] ? kp_mkout<4 > ? ad14 aa13 gpio<108 > icoc z gpio<108> cif_dd<7> ? ? pd-0 note[1] note [3] chout<0> kp_mkout<5 > ? d17 d16 gpio<109 > icoc z gpio<109> mmdat<1> mssdio ? pd-0 note[1] note [3] mmdat<1> mssdio ? b17 c15 gpio<110 > icoc z gpio<110> mmdat<2>/ mmccs<0> ?? pd-0 note[1] note [3] mmdat<2>/ mmccs<0> ?? c17 a17 gpio<111 > icoc z gpio<111> mmdat<3>/ mmccs<1> ?? pd-0 note[1] note [3] mmdat<3>/ mmccs<1> ?? b18 b16 gpio<112 > icoc z gpio<112> mmcmd nmsins ? pd-0 note[1] note [3] mmcmd ? ? a13 a10 gpio<113 > icoc z gpio<113> ??usb_p3_3 pd-0 note[1] note [3] i2s_sysclk ac97_reset_n ? d24 f19 gpio<114 > note [17] icoc z gpio<114> note [17] cifdd_<1> ?? pd-0 note[1] note [3] uvs0 ? e21 e21 gpio<115 > note [17] icoc z gpio<115> note [17] dreq<0> cif_dd<3> mbreq pu-1 note[1] note [3] uen nuvs1 pwm_out <1> c24 e20 gpio<116 > icoc z gpio<116> cif_dd<2> ac97_sdata_i n_0 udet pu-1 note[1] note [3] dval<0> nuvs2 mbgnt d20 c18 gpio<117 > icoc z gpio<117> scl ? ? pu-1 note[1] note [3], note[12] scl ? ? table 4-1. pin usage summary (sheet 10 of 17) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4-2 for numbered notes on reset and sleep states.
4-20 electrical, mechanical, and thermal specification intel? PXA270 processor pin listing and si gnal definitions a22 b20 gpio<118 > icoc z gpio<118> sda ? ? pu-1 note[1] note [3], note[12] sda ? ? vcc_usb b22 d18 usbc_p iaoa z usbc_p usbc_p ? ? hi-z hi-z c20 e19 usbc_n iaoa z usbc_n usbc_n ? ? hi-z hi-z e22 e22 usbh_p <1> iaoa z usbh_p<1 > usbh_p<1> ? ? hi-z hi-z d23 d22 usbh_n <1> iaoa z usbh_n<1 > usbh_n<1> ? ? hi-z hi-z vcc_usim f22 h19 gpio<90> icoc z gpio<90> kp_mkin<5> usb_p3_5 cif_dd<4> pd-0 note[1] note [3] ?nurst? f23 g19 gpio<91> icoc z gpio<91> kp_mkin<6> usb_p3_1 cif_dd<5> pd-0 note[1] note [3] ?uclk? e23 f20 uio icoc z uio uio ? ? driven low hi-z vcc_reg v22 u20 gpio<0> icoc z gpio<0> gpio<0> ? ? pd-0 note[1] note [3] y24 u21 gpio<1> icoc z gpio<1> gpio<1> ? ? pu-1 note[1] note [7] w21 v22 gpio<3> icoc z gpio<3> pwr_scl ? ? pu-1 note[1] hi-z w23 t19 gpio<4> icoc z gpio<4> pwr_sda ? ? pu-1 note[1] hi-z u22 t22 gpio<9> note [18] icoc z gpio<9> note [18] ? ? ffcts pd-0 note[1] note [7] hz_clk ? chout<0> v23 u22 gpio<10> note [18] icoc z gpio<10> note [18] ffdcd ?usb_p3_5 pd-0 note[1] note [7] hz_clk ? chout<1> pd-0 note[1] note [7] w24 t21 clk_req icoc z clk_req clk_req ? ? pu-1 note [8] y22 w20 nreset ic nreset nreset ? ? input - note [9] input y21 w21 nreset_ out oc nreset_o ut nreset_out ? ? low note [8] ab23 v19 boot_se l ic boot_sel boot_sel ? ? input input table 4-1. pin usage summary (sheet 11 of 17) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4-2 for numbered notes on reset and sleep states.
electrical, mechanical, and thermal specification 4-21 intel? PXA270 processor pin listing and si gnal definitions y23 w22 pwr_en oc pwr_en pwr_en ? ? note[16] note [8] ab24 u19 nbatt_f ault ic nbatt_fau lt nbatt_fault ? ? low input w22 v20 nvdd_f ault ic nvdd_fau lt nvdd_fault ? ? low input aa24 v21 sys_en icoc z sys_en sys_en ? ? ? note [7] ab21 y19 pwr_ca p<0> oa ? pwr_cap<0> ? ? ? note [7] ad22 aa21 pwr_ca p<1> oa ? pwr_cap<1> ? ? ? note [7] ac22 y18 pwr_ca p<2> oa ? pwr_cap<2> ? ? ? note [7] aa20 w17 pwr_ca p<3> oa ? pwr_cap<3> ? ? ? note [7] u21 t20 ntrst ic ntrst ntrst ? ? input - note [9] input u23 r22 tdi ic tdi tdi ? ? input - note [9] input v24 r21 tdo ocz tdo tdo ? ? hi-z hi-z t21 r20 tms ic tms tms ? ? input - note [9] input t22 r19 tck ic tck tck ? ? input input t23 p22 testclk ic testclk testclk ? ? pd-0 input vcc_osc ac21 ab20 pxtal_i n ia pxtal_in pxtal_in ? ? note[2] note [2] ad21 aa20 pxtal_o ut oa pxtal_ou t pxtal_out ? ? note[2] note [2] aa22 y21 txtal_i n ia txtal_in txtal_in ? ? note[2] note [2] aa23 y22 txtal_o ut oa txtal_ou t txtal_out ? ? note[2] note [2] ab22 w19 pwr_ou t oa pwr_out pwr_out ? ? hi-z hi-z supplies ab20 y17 vcc_bat t ps vcc_batt vcc_batt ? ? input input a12 b10 vcc_io ps vcc_io vcc_io ? ? input input ad17 w15 vcc_io ps vcc_io vcc_io ? ? input input a16 d14 vcc_io ps vcc_io vcc_io ? ? input input b24 a21 vcc_usb ps vcc_usb vcc_usb ? ? input input table 4-1. pin usage summary (sheet 12 of 17) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4-2 for numbered notes on reset and sleep states.
4-22 electrical, mechanical, and thermal specification intel? PXA270 processor pin listing and si gnal definitions a24 a22 vcc_usb ps vcc_usb vcc_usb ? ? input input a23 b22 vcc_usb ps vcc_usb vcc_usb ? ? input input b23 d19 vcc_usb ps vcc_usb vcc_usb ? ? input input p24 m19 vcc_lc d ps vcc_lcd0 vcc_lcd ? ? input input j24 j21 vcc_lc d ps vcc_lcd1 vcc_lcd ? ? input input p1 b2 vcc_me m ps vcc_mem vcc_mem ? ? input input c3 c3 vcc_me m ps vcc_mem vcc_mem ? ? input input e2 c6 vcc_me m ps vcc_mem vcc_mem ? ? input input l3 c9 vcc_me m ps vcc_mem vcc_mem ? ? input input ad2 f3 vcc_me m ps vcc_mem vcc_mem ? ? input input ac2 h3 vcc_me m ps vcc_mem vcc_mem ? ? input input ac1 k3 vcc_me m ps vcc_mem vcc_mem ? ? input input ad1 m3 vcc_me m ps vcc_mem vcc_mem ? ? input input m1 p3 vcc_me m ps vcc_mem vcc_mem ? ? input input h1 t3 vcc_me m ps vcc_mem vcc_mem ? ? input input f1 v3 vcc_me m ps vcc_mem vcc_mem ? ? input input ad8 y3 vcc_me m ps vcc_mem vcc_mem ? ? input input u2 y5 vcc_me m ps vcc_mem vcc_mem ? ? input input aa2 y7 vcc_me m ps vcc_mem vcc_mem ? ? input input ac8 y9 vcc_me m ps vcc_mem vcc_mem ? ? input input b8 aa2 vcc_me m ps vcc_mem vcc_mem ? ? input input a4 n/a vcc_me m ps vcc_mem vcc_mem ? ? input input ac6 n/a vcc_me m ps vcc_mem vcc_mem ? ? input input table 4-1. pin usage summary (sheet 13 of 17) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4-2 for numbered notes on reset and sleep states.
electrical, mechanical, and thermal specification 4-23 intel? PXA270 processor pin listing and si gnal definitions w2 n/a vcc_me m ps vcc_mem vcc_mem ? ? input input ad12 aa11 vcc_bb ps vcc_bb vcc_bb ? ? input input ac20 ab19 vcc_pll ps vcc_pll vcc_pll ? ? input input a9 b4 vcc_sra m ps vcc_sram vcc_sram ? ? input input a8 b7 vcc_sra m ps vcc_sram vcc_sram ? ? input input a5 b8 vcc_sra m ps vcc_sram vcc_sram ? ? input input b4 c5 vcc_sra m ps vcc_sram vcc_sram ? ? input input b12 d11 vcc_co re ps vcc_core vcc_core ? ? input input a7 e6 vcc_co re ps vcc_core vcc_core ? ? input input d3 e8 vcc_co re ps vcc_core vcc_core ? ? input input j23 f5 vcc_co re ps vcc_core vcc_core ? ? input input l24 h5 vcc_co re ps vcc_core vcc_core ? ? input input f24 l4 vcc_co re ps vcc_core vcc_core ? ? input input ad16 e15 vcc_co re ps vcc_core vcc_core ? ? input input r24 e17 vcc_co re ps vcc_core vcc_core ? ? input input m23 f18 vcc_co re ps vcc_core vcc_core ? ? input input b21 h18 vcc_co re ps vcc_core vcc_core ? ? input input w3 l19 vcc_co re ps vcc_core vcc_core ? ? input input ad4 r5 vcc_co re ps vcc_core vcc_core ? ? input input t2 u5 vcc_co re ps vcc_core vcc_core ? ? input input ad11 v6 vcc_co re ps vcc_core vcc_core ? ? input input n/a v8 vcc_co re ps vcc_core vcc_core ? ? input input n/a w11 vcc_co re ps vcc_core vcc_core ? ? input input table 4-1. pin usage summary (sheet 14 of 17) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4-2 for numbered notes on reset and sleep states.
4-24 electrical, mechanical, and thermal specification intel? PXA270 processor pin listing and si gnal definitions n/a r18 vcc_co re ps vcc_core vcc_core ? ? input input n/a u18 vcc_co re ps vcc_core vcc_core ? ? input input n/a v15 vcc_co re ps vcc_core vcc_core ? ? input input n/a v17 vcc_co re ps vcc_core vcc_core ? ? input input e24 f21 vcc_usi m ps vcc_usim vcc_usim ? ? input input aa21 w18 vss ps vss vss ? ? input input ac24 y20 vss ps vss vss ? ? input input ad24 aa22 vss ps vss vss ? ? input input ac23 ab21 vss ps vss vss ? ? input input ad23 ab22 vss ps vss vss ? ? input input v21 n/a vss ps vss vss ? ? input input d11 b12 vss_io ps vss_io vss_io ? ? input input aa19 b15 vss_io ps vss_io vss_io ? ? input input d15 b18 vss_io ps vss_io vss_io ? ? input input n21 d21 vss_io ps vss_io vss_io ? ? input input aa16 h21 vss_io ps vss_io vss_io ? ? input input h21 m21 vss_io ps vss_io vss_io ? ? input input f21 n19 vss_io ps vss_io vss_io ? ? input input d18 aa14 vss_io ps vss_io vss_io ? ? input input u24 aa18 vss_io ps vss_io vss_io ? ? input input d5 a1 vss_me m ps vss_mem vss_mem ? ? input input f4 a2 vss_me m ps vss_mem vss_mem ? ? input input h4 b1 vss_me m ps vss_mem vss_mem ? ? input input j4 b3 vss_me m ps vss_mem vss_mem ? ? input input ac3 b6 vss_me m ps vss_mem vss_mem ? ? input input ab2 b9 vss_me m ps vss_mem vss_mem ? ? input input l4 f2 vss_me m ps vss_mem vss_mem ? ? input input t4 h2 vss_me m ps vss_mem vss_mem ? ? input input table 4-1. pin usage summary (sheet 15 of 17) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4-2 for numbered notes on reset and sleep states.
electrical, mechanical, and thermal specification 4-25 intel? PXA270 processor pin listing and si gnal definitions v4 l2 vss_me m ps vss_mem vss_mem ? ? input input aa5 p2 vss_me m ps vss_mem vss_mem ? ? input input aa8 t2 vss_me m ps vss_mem vss_mem ? ? input input aa9 v2 vss_me m ps vss_mem vss_mem ? ? input input d9 aa1 vss_me m ps vss_mem vss_mem ? ? input input n4 aa6 vss_me m ps vss_mem vss_mem ? ? input input r2 aa9 vss_me m ps vss_mem vss_mem ? ? input input c5 ab1 vss_me m ps vss_mem vss_mem ? ? input input y4 ab2 vss_me m ps vss_mem vss_mem ? ? input input aa13 ab11 vss_bb ps vss_bb vss_bb ? ? input input ad20 aa19 vss_pll ps vss_pll vss_pll ? ? input input b2 e5 vss_cor e ps vss_core vss_core ? ? input input a2 e7 vss_cor e ps vss_core vss_core ? ? input input b1 e9 vss_cor e ps vss_core vss_core ? ? input input a1 g5 vss_cor e ps vss_core vss_core ? ? input input j21 j5 vss_cor e ps vss_core vss_core ? ? input input d10 e14 vss_cor e ps vss_core vss_core ? ? input input aa15 e16 vss_cor e ps vss_core vss_core ? ? input input m21 e18 vss_cor e ps vss_core vss_core ? ? input input u3 g18 vss_cor e ps vss_core vss_core ? ? input input aa7 j18 vss_cor e ps vss_core vss_core ? ? input input p21 p5 vss_cor e ps vss_core vss_core ? ? input input k21 t5 vss_cor e ps vss_core vss_core ? ? input input table 4-1. pin usage summary (sheet 16 of 17) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4-2 for numbered notes on reset and sleep states.
4-26 electrical, mechanical, and thermal specification intel? PXA270 processor pin listing and si gnal definitions g21 v5 vss_cor e ps vss_core vss_core ? ? input input d21 v7 vss_cor e ps vss_core vss_core ? ? input input d12 v9 vss_cor e ps vss_core vss_core ? ? input input d8 p18 vss_cor e ps vss_core vss_core ? ? input input w4 t18 vss_cor e ps vss_core vss_core ? ? input input aa12 v14 vss_cor e ps vss_core vss_core ? ? input input b5 v16 vss_cor e ps vss_core vss_core ? ? input input d7 v18 vss_cor e ps vss_core vss_core ? ? input input table 4-1. pin usage summary (sheet 17 of 17) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4-2 for numbered notes on reset and sleep states.
electrical, mechanical, and thermal specification 4-27 intel? PXA270 processor pin listing and si gnal definitions 4.3 signal types table 4-2. pin usage and mapping notes note description [1] gpio reset/deep sleep operation: after any reset is asserted or if the pxa2 70 processor is in deep sleep mode, these pins are configured as gpio inputs by default. the input buffers for these pins are disabled to prevent current drain and must be enabled prior to use by clearing the read disable hold bit, pssr[rdh]. until rdh is cl eared, each pin is pulled high (pu-1), pulled low (pd-0), or floated (hi-z). [2] crystal oscillator pins: these pins connect the external crystals to the on-chip oscillators and are not affected by either reset or sleep. for more information, see the ?clocks and power? chapter in the intel? pxa27x processor family developer?s manual . [3] gpio sleep operation: during the transition into sleep mode, the confi guration of these pins is determined by the corresponding gpio setting. this pin is not driven during sleep if the direction of the pin is selected to be an input. if the direction of the pin is selected as an output, the value contained in the power manager gpio sleep-state register (pgsr0/1/2/3) is driven out onto the pin and hel d while the PXA270 processor is in sleep mode. upon exit from sleep mode, gpios that are configured as out puts continue to hold the standby, sleep, or deep-sleep state until software clears the peripheral control hold bit, pssr[ph]. soft ware must clear this bit (by writing 0b1 to it) after the peripherals have been fully configured, as described in no te[1], but before the process actually uses them. gpios that are configured as inputs immediately after exiting sleep mode cannot be used until pssr[rdh] is cleared. [4] static memory control pins: during sleep mode, these pins can be progra mmed either to drive the value in the power manager gpio sleep-state register (pgsr0/1/2/3) or to be plac ed in a hi-z (undriven) state. to select the hi-z state, software must set pcfr[fs]. if fs is not set, these pins f unction as described in note[3] during the transition to sleep mode. [5] pcmcia control pins: during sleep mode, these pins can be programmed either to drive the value in the power manager gpio sleep-state register (pgsr0/1/2/3) or to be placed in a hi-z (undriven) state. to select the hi-z state, software must set pcfr[fp]. if fp is not set, these pins function as described in note[3] during the transition to sleep mode. [6] (reserved) [7] when the power manager overrides the gpio alternate f unction, the power manager gpio sleep-state registers (pgsr0/1/2/3) and the pssr[rdh] bit are ignored. pullup and pulldown are disabled immediately after the power manager overrides the gpio function. [8] output functions during sleep mode [9] pull-up always enabled [10] (reserved) [11] pins do not function during sleep m ode if the os timer is active [12] pins must be floated by software during sleep mode (floating does not happen automatically) [13] (reserved) [14] (reserved) [15] the pin is three-stateable (hi-z) based on the value of pc fr[fs]. there is no pgsr0/1/2/3 setting associated with the pin because it is not a gpio. [16] pwr_en goes high during reset, between the assertion of the re set pin and the de-assertion of internal reset within the PXA270 processor, after sys_en is driven high. [17] gpios 114 and115: the alternate function configuration of these pins is ignored when either pucr[usim114] or pucr[usim115] bits are set. setting these bits forces the usim enable signal onto these gpios. [18] when software sets the oscc[pio_en] or oscc[tout_en] bi ts, then any gpio alternate function setting applied to gpio<9> or gpio <10> is overridden with the clk_ pio function on gpio<9> and clk_tout on gpio<10>. [19] refer to ta b l e 4 - 4 .
4-28 electrical, mechanical, and thermal specification intel? PXA270 processor pin listing and si gnal definitions 4.4 memory controller reset and initialization on reset, the sdram interface is disabled. reset values for th e boot rom are determined by boot_sel (see the intel? pxa27x processor family developers manual , memory controller chapter). boot rom is immediatel y available for reading upon exit from reset, and all memory interface control registers are available for writing. on hardware reset, the memory pins a nd controller are in the state shown in table 4-4 . table 4-3. signal types type description ic cmos input oc cmos output ocz cmos output, three-stateable icocz cmos bidirectional, three-stateable ia analog input oa analog output iaoa analog bidirectional iaoaz analog bidirectional - three-stateable ps power supply table 4-4. memory controller pin reset values (sheet 1 of 2) pin name reset, sleep, standby, deep-sleep, frequency change, and manual self-refresh mode values sdclk <3 1 :0> 0b000 sdcke 0 dqm <3:0> 0b0000 nsdcs <3:2> gpio (memory controller drives 0b11) ? nsdcs <1:0> 0b11 nwe 1 nsdras 1 nsdcas 1 noe 1 ma <25:0> 0x0000_0000 1 rdnwr 0 md <31:0> 0x0000_0000 2 ncs <0> 1 ncs <5:1> gpio (memory controller drives 0b11111) npioir gpio (memory controller drives high) npioiw gpio (memory controller drives high)
electrical, mechanical, and thermal specification 4-29 intel? PXA270 processor pin listing and si gnal definitions the address signals are driven low and data sign als are pulled low during sleep, standby, deep- sleep, frequency-change modes, and manual self-r efresh. all other memory control signals are in the same state that they are in after a hardware re set. if the sdrams are in self-refresh mode, they are kept there by driving sdcke low. 4.5 power-supply pins table 4-5 summarize the power-supply ball count. npoe gpio (memory cont roller drives high) npwe gpio (memory cont roller drives high) note: ? this indicates that the gpio pin, if configured for the alternate function used by the memory controller during reset, drives the represented value. note: sclk<3> is only available on PXA270 processor family packages 1. ma pins are driven 2. md pins are pulled low table 4-4. memory controller pin reset values (sheet 2 of 2) pin name reset, sleep, standby, deep-sleep, frequency change, and manual self-refresh mode values table 4-5. discrete (13x13 vf-bga) power supply pin summary name number of package balls 13x13 mm vf-bga number of pachage balls 23x23 mm pbga vcc_batt 11 vcc_io 33 vcc_usb 44 vcc_lcd 22 vcc_mem 19 16 vcc_bb 11 vcc_pll 11 vcc_sram 44 vcc_core 14 20 vcc_usim 11 vss 65 vss_io 99 vss_mem 17 17 vss_bb 11 vss_pll 11 vss_core 56 56
4-30 electrical, mechanical, and thermal specification intel? PXA270 processor pin listing and si gnal definitions
electrical, mechanical, and thermal specification 5-1 electrical specifications 5 5.1 absolute maximum ratings the absolute maximum ratings (shown in table 5-1 ) define limitations for electrical and thermal stresses. these limits prev ent permanent damage to th e intel? PXA270 processor. note: absolute maximum ratings are not operating ranges. 5.2 operating conditions this section shows operating voltage, frequency, and temperature specifications for the PXA270 processor. table 5-1. absolute maximum ratings symbol description min max units t s storage temperature ?40 125 c v cc_ol1 offset voltage between any of the following pins: vcc_core ?0.3 0.3 v v cc_ol2 offset voltage between any of the following pins: vcc_sram ?0.3 0.3 v v cc_oh1 offset voltage between any of the following pins: vcc_mem ?0.3 0.3 v v cc_oh2 offset voltage between any of the following pins: vcc_io ?0.3 0.3 v v cc_oh3 offset voltage between vcc_lcd<0> and vcc_lcd<1> ?0.3 0.3 v v cc_hv voltage applied to high-voltage supply pins (vcc_bb, vcc_usb, vcc_usim, vcc_mem, vcc_io<, vcc_lcd) vss?0.3 vss+4.0 v v cc_lv voltage applied to low-voltage supply pins (vcc_core, vcc_pll, vcc_sram) vss?0.3 vss+1.45 v v ip voltage applied to non-supply pins except pxtal_in, pxtal_out, txtal_in, and txtal_out pins vss?0.3 vss+4.0 v v ip_x voltage applied to xtal pins (pxtal_in, pxtal_out, txtal_in, txtal_out) vss?0.3 vss+1.45 v v esd maximum esd stress voltage, three stresses maximum: ? any pin to any supply pin, either polarity, or ? any pin to all non-supply pi ns together, either polarity ? 2000 v i eos maximum dc input current (electrical overstress) for any non-supply pin ? 5 ma
5-2 electrical, mechanical, and thermal specification intel? PXA270 processor electrical specifications table 5-2 shows each power domain s supported voltages (e xcept for vcc_mem and vcc_core). table 5-3 shows all of the supported memory voltages and frequency operating ranges (vcc_mem). table note: shows all of the supported core voltage and frequency ranges (vcc_core). the operating temperature specification is a function of voltage and frequency. table 5-2. voltage, temperature, and frequen cy electrical specifications (sheet 1 of 2) symbol description min typical max units operating temperature tc a s e package operating temperature ? (standard te m p ) -25 ? +85 c package operating temperature ? (extended temp - pbga only) -40 ? +85 theta jc junction-to-case temperature gradient (vf-bga) ? 2 ? c / watt junction-to-case temperature gradient (pbga) ? 1.4 ? vcc_batt voltage vvcc0 voltage applied on vcc_batt @3.0v 2.25 3.00 3.75 v vvdf1 voltage difference between vcc_batt and vcc_io during power-on reset or deep-sleep wake-up (from the assertion of sys_en to the de-assertion of nreset_out) 0 ? 0.30 v vvdf2 voltage difference between vcc_batt and vcc_io when vcc_io is enabled 0 ? 0.20 v tbramp ramp rate ? 10 12 mv/us vcc_pll voltage vvcc1 voltage applied on vcc_pll @1.3v (+10 / -10%) 1.17 1.30 1.43 v tpwrramp ramp rate ? 10 12 mv/us vcc_bb voltages vvcc2a voltage applied on vcc_bb @1.8v (+20 / -5%) 1.71 1.80 2.16 v vvcc2b voltage applied on vcc_bb @2.5v (+10 / -10%) 2.25 2.50 2.75 v vvcc2c voltage applied on vcc_bb @3.0v (+10 / -10%) 2.70 3.0 3.30 v vvcc2d voltage applied on vcc_bb @3.3v (+10 / -10%) 2.97 3.3 3.63 v tsysramp ramp rate ? 10 12 mv/us vcc_lcd voltages vvcc3a voltage applied on vcc_lcd @1.8v (+20 / -5%) 1.71 1.80 2.16 v
electrical, mechanical, and thermal specification 5-3 intel? PXA270 processor electrical specifications table 5-3 shows the supported memory frequency and memory supply voltage operating ranges for the PXA270 processor. vvcc3b voltage applied on vcc_lcd @2.5v (+10 / -10%) 2.25 2.50 2.75 v vvcc3c voltage applied on vcc_lcd @3.0v (+10 / -10%) 2.70 3.0 3.30 v vvcc3d voltage applied on vcc_lcd @3.3v (+10 / -10%) 2.97 3.3 3.63 v tsysramp ramp rate ? 10 12 mv/us vcc_io voltages vvcc4a voltage applied on vcc_io @3.0v (+10 / -10.3%) 2.69175 3.0 3.30 v vvcc4b voltage applied on vcc_io @3.3v (+10 / -10%) 2.97 3.3 3.63 v tsysramp ramp rate ? 10 12 mv/us note: vcc_io must be maintained at a voltage as high as or higher than, all other supplies except for vcc_batt and vcc_usb vcc_usim voltages vvcc5a voltage applied on vcc_usim @1.8v (+20 / -5%) 1.71 1.80 2.16 v vvcc5b voltage applied on vcc_usim @3.0v (+10 / -10%) 2.70 3.0 3.30 v tsysramp ramp rate ? 10 12 mv/us note: if the system does not use the usim module, vc c_usim can be tied to vcc_io (at any supported vcc_io voltage level). this allows the gpio?s on vcc_usim to be used at the same voltage level as vcc_io gpio?s. note: software must not configure usim signals to be used if this is done. vcc_sram voltage vvcc6 voltage applied on vcc_sram @1.1v (+10 / -10%) 0.99 1.10 1.21 v tpwrramp ramp rate ? 10 12 mv/us vcc_usb voltage vvcc7a voltage applied on vcc_usb @3.0v (+10 / -10%) 2.70 3.00 3.30 v vvcc7b voltage applied on vcc_usb @3.3v (+10 / -10%) 2.97 3.30 3.63 v tsysramp ramp rate ? 10 12 mv/us ? system design must ensure that the device case temper ature is maintained within the specified limits. in some system applications it may be necessary to use external thermal management (for example, a package-mounted heat spreader) or configure the devic e to limit power consumption and maintain acceptable case temperatures. table 5-2. voltage, temperature, and frequency electrical specifications (sheet 2 of 2) symbol description min typical max units
5-4 electrical, mechanical, and thermal specification intel? PXA270 processor electrical specifications table 5-3. memory voltage and frequency electrical specifications table 5-4 shows the supported core frequency and core supply voltage operating ranges for the PXA270 processor. each frequency range is specified in the following format: (core frequency/internal system bus frequency/ memory controller frequency/sdram frequency) note: refer to the ?clocks and power? section of the intel? pxa27x proce ssor family developers manual for supported frequencies, clock re gister settings as listed in table 5-4 . symbol description min typical max units memory voltage and frequency range 1 vmem1 voltage applied on vcc_mem 1.71 1.80 2.16 v fsm1a external synchronous memory frequency, sdclk1, sdclk2 13 ? 104 mhz fsm1b external synchronous memory frequency, sdclk0 13 ? 104 mhz tsysramp ramp rate ? 10 12 mv/us memory voltage and frequency range 2 vmem2 voltage applied on vcc_mem 2.25 2.50 2.75 v fsm2a external synchronous memory frequency, sdclk1, sdclk2 13 ? 104 mhz fsm2b external synchronous memory frequency, sdclk0 13 ? 104 mhz tsysramp ramp rate ? 10 12 mv/us memory voltage and frequency range 3 vmem3 voltage applied on vcc_mem 2.70 3.0 3.3 v fsm3a external synchronous memory frequency, sdclk1, sdclk2 13 ? 104 mhz fsm3b external synchronous memory frequency, sdclk0 13 ? 104 mhz tsysramp ramp rate ? 10 12 mv/us memory voltage and frequency range 4 vmem4 voltage applied on vcc_mem 2.97 3.30 3.63 v fsm4a external synchronous memory frequency, sdclk1, sdclk2 13 ? 104 mhz fsm4b external synchronous memory frequency, sdclk0 13 ? 104 mhz tsysramp ramp rate ? 10 12 mv/us table 5-4. core voltage and frequency electrical specifications (sheet 1 of 2) symbol description min typical max units core voltage and frequency range 1 (13/13/13/13) vvccc1 voltage applied on vcc_core 0.8075 0.85 1.705 v fcore1 core operating frequency 13 ? 13 mhz tpwrramp ramp rate ? 10 12 mv/us
electrical, mechanical, and thermal specification 5-5 intel? PXA270 processor electrical specifications core voltage and frequency range 2 (91/45.5/91/45.5) and (104/104/104/104) vvccc2 voltage applied on vcc_core 0.855 0.9 1.705 v fcore2 core operating frequency 91 ? 104 mhz tpwrramp ramp rate ? 10 12 mv/us core voltage and frequency range 3 (156/104/104/104) vvccc3 voltage applied on vcc_core 0.95 1.00 1.705 v fcore3 core operating frequency ? 156 ? mhz tpwrramp ramp rate ? 10 12 mv/us core voltage and frequency range 4 (208/208/208/104) vvccc4 voltage applied on vcc_core 1.0925 1.15 1.705 v fcore4 core operating frequency ? 208 ? mhz tpwrramp ramp rate ? 10 12 mv/us core voltage and frequency range 4a (208/104/104/104) vvccc4a voltage applied on vcc_core 0.9975 1.05 1.705 v fcore4a core operating frequency ? 208 ? mhz tpwrramp ramp rate ? 10 12 mv/us core voltage and frequency range 5 (312/208/208/104) vvccc5 voltage applied on vcc_core 1.1875 1.25 1.705 v fcore5 core operating frequency ? 312 ? mhz tpwrramp ramp rate ? 10 12 mv/us core voltage and frequency range 5a (312/104/104/104) vvccc5a voltage applied on vcc_core 0.99 1.1 1.705 v fcore5a core operating frequency ? 312 ? mhz tpwrramp ramp rate ? 10 12 mv/us core voltage and frequency range 6 (416/208/208/104) vvccc6 voltage applied on vcc_core 1.2825 1.35 1.705 v fcore6 core operating frequency ? 416 ? mhz tpwrramp ramp rate ? 10 12 mv/us core voltage and frequency range 7 (520/208/208/104) vvccc7 voltage applied on vcc_core 1.3775 1.45 1.705 v fcore7 core operating frequency ? 520 ? mhz tpwrramp ramp rate ? 10 12 mv/us core voltage and frequency range 8 (624/208/208/104) ? vvccc8 voltage applied on vcc_core 1.4725 1.55 1.705 v fcore8 core operating frequency ? 624 ? mhz tpwrramp ramp rate ? 10 12 mv/us ?core operating frequency not offered in pbga package. table 5-4. core voltage and frequency electrical specifications (sheet 2 of 2)
5-6 electrical, mechanical, and thermal specification intel? PXA270 processor electrical specifications 5.2.1 internal power domains the external power supplies are used to generate several internal power domains, which are shown in table 5-5 . refer to the power manager / internal power domain block diagram in the ?clocks and power? section of the intel? pxa27x processor family developers manual for more information on internal power domains. table 5-5. internally generated power domain descriptions table 5-6 shows the recommended core voltage speci fication for each of the lower power modes. table 5-6. core voltage specifications for lower power modes 5.3 power-consumption specifications power consumption depends on the operating voltage and frequency, peripherals enabled, external switching activity, and extern al loading and other factors. table 5-7 contains the power consumption information. there are three sets of data: active power consumption, idle power consumption and low power modes power consumption. data was taken at room temperature. for active power c onsumption data, no peripherals are enabled except for uart. name units generation tolerance vcc_reg io associated with deep-sleep- active units switched between vcc_batt and vcc_io - vcc_osc oscillator power supplies generated from vcc_reg +/- 30% vcc_rtc rtc and power manager supply switched between vcc_osc and vcc_core - vcc_pi power manager i 2 c supply switched between vcc_osc and vcc_core - vcc_cpu cpu core independent power-down from vcc_core - vcc_per peripheral units independent power-down from vcc_core - vcc_rx particular internal sram unit switched between vcc_osc and vcc_sram - mode description min typical max units standby voltage applied on vcc_core 1.045 1.1 1.21 v deep-idle voltage applied on vcc_core 0.8075 0.85 0.935 v
electrical, mechanical, and thermal specification 5-7 intel? PXA270 processor electrical specifications table 5-7. power-consumption specifications (sheet 1 of 2) parameter description typical units conditions active power consumption 520 mhz active power (208 mhz system bus) 747 mw vcc_core = 1.45v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 416 mhz active power (208 mhz system bus) 570 mw vcc_core = 1.35v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 312 mhz active power (208 mhz system bus) 390 mw vcc_core = 1.25v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 312 mhz active power (104 mhz system bus) 375 mw vcc_core = 1.1v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 208 mhz active power (208 mhz system bus) 279 mw vcc_core = 1.15v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 104 mhz active power (104 mhz system bus) 116 mw vcc_core = 0.9v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 13 mhz active power (cccr[cpdis=1) 44.2 mw vcc_core = 0.85v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v idle power consumption 520 mhz idle power (208 mhz system bus) 222 mw vcc_core = 1.45v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 416 mhz idle power (208 mhz system bus) 186 mw vcc_core = 1.35v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 312 mhz idle power (208 mhz system bus) 154 mw vcc_core = 1.25v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 312 mhz idle power (104 mhz system bus) 109 mw vcc_core = 1.1v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 208 mhz idle power (208 mhz system bus) 129 mw vcc_core = 1.15v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 104 mhz idle power (104 mhz system bus) 64 mw vcc_core = 0.9v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v low power modes power consumption 13 mhz idle mode 1 power (lcd on) 15.4 mw vcc_core, vcc_sram, vcc_pll = 0.85v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v
5-8 electrical, mechanical, and thermal specification intel? PXA270 processor electrical specifications 5.4 dc specification the dc characteristics for each pin include input sense levels, output drive levels, and currents. these parameters can be used to determine maximum dc loading and to determine maximum transition times for a given load. table 5-8 shows the dc operating conditions for the high- and low-strength input, output, and i/o pins. note: vcc_io must be maintained at a voltage as hi gh as or higher than all other supplies except vcc_batt and vcc_usb and vcc_usb. 13 mhz idle mode 1 power (lcd off) 8.5 mw vcc_core, vcc_sram, vcc_pll = 0.85v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v deep-sleep mode 0.1014 mw vcc_core, vcc_sram, vcc_pll = 0v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v sleep mode 0.1630 mw vcc_core, vcc_sram, vcc_pll = 0v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v standby mode 1.7224 mw vcc_core, vcc_sram, vcc_pll = 1.1v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v note: 1) 13 mhz idle mode (cccr[cpdis] =1 (cccr[ppdis] = 1) table 5-7. power-consumption specifications (sheet 2 of 2) parameter description typical units conditions table 5-8. standard input, output, and i/o pin dc operating conditions (sheet 1 of 2) symbol description min max unit s testing conditions / notes input dc operating conditions (vcc = 1.8v, 2.5, 3.0, 3.3 typical) vih 1 input high voltage, all standard input and i/o pins, relative to applicable vcc (vcc_io, vcc_mem, vcc_bb, vcc_lcd, vcc_usb, or vcc_usim) 0.8 * vcc vcc + 0.1 v ? vil 1 input low voltage, all standard input and i/o pins, relative to applicable vss (vss_io, vss_mem, or vss_bb) and vcc (vcc_io, vcc_mem, vcc_bb, vcc_lcd, vcc_usb, or vcc_usim) vss - 0.1 0.2 * vcc v ? os dc overshoot voltage / duration ? +1 v max duration of 4ns us dc undershoot voltage / duration ? -1 v max duration of 4ns output dc operating conditions (vcc = 1.8, 2.5, 3.0, 3.3 typical)
electrical, mechanical, and thermal specification 5-9 intel? PXA270 processor electrical specifications 5.5 oscillator electrical specifications the PXA270 processor contains two oscillato rs: a 32.768-khz oscillator and a 13.000-mhz oscillator. each oscillator requires a specific crystal. 5.5.1 32.768-khz osci llator specifications the 32.768 - khz oscillator is connected between the txtal_in (amplifier input) and txtal_out (amplified output). table 5-9 and table 5-10 list the appropriate 32.768 - khz specifications. to drive the 32.768 - khz crystal pins from an external source: 1. drive the txtal_in pin with a digital signal that has low and high levels as listed in table 5-10 . do not exceed vcc_pll or go belo w vss_pll by more than 100 mv. the minimum slew rate is 1 volt per 1 s. the ma ximum current drawn from the external clock source when the clock is at its maximum positive voltage is typically 1 ma. 2. float the txtal_out pin or drive it in complement to the txtal_in pin, with the same voltage level and slew rate. caution: the txtal_in and txtal_out pins must not be driven from an external source if the PXA270 processor sleep / deep sleep dc-dc converter is enabled. voh 1 output high voltage, all standard output and i/ o pins, relative to applicable vcc (vcc_io, vcc_mem, vcc_bb, vcc_lcd, vcc_usb, or vcc_usim) vcc - 0.3 vcc v ioh = -4 ma 2 , -3 ma 3 vol 1 output low voltage, all standard output and i/o pins, relative to applicable vss (vss_io, vss_mem, or vss_bb) vss vss + 0.3 v ioh = 4 ma 2 , 3 ma 3 notes: 1. programmable drive strengths set to 0x 5 for memory and lcd programmable signals. 2. the current for the high-strength pins are ma<25:0>, md< 31:0>, noe, nwe, nsdras, nsdcas, dqm<3:0>, nsdcs<3:0>, sdcke<1>, sdclk<3:0>, rdnwr, ncs<5:0>, and npwe. 3. the current for all other output and i/o pins are low strength. table 5-8. standard input, output, and i/o pin dc operating conditions (sheet 2 of 2) symbol description min max unit s testing conditions / notes table 5-9. typical 32.768-khz crystal requirements (sheet 1 of 2) parameter minimum typical maximum units frequency range ? 32.768 ? khz frequency tolerance ?30 ? +30 ppm frequency stability, parabolic coefficient ? ? ?0.04 ppm/ ( ? c ) 2 drive level ? ? 1.0 uw load capacitance (c l ) ? 12.5 ? pf shunt capacitance (c o )?0.9?pf
5-10 electrical, mechanical, and thermal specification intel? PXA270 processor electrical specifications motional capacitance (c i )?2.1?ff equivalent series resistance (r s )?1835k ? insulation resistance at 100 v dc 100 ? ? m ? aging, at operating temperature per year ? ? 3.0 ppm table 5-9. typical 32.768-khz crystal requirements (sheet 2 of 2) parameter minimum typical maximum units
electrical, mechanical, and thermal specification 5-11 intel? PXA270 processor electrical specifications 5.5.2 13.000-mhz osc illator specifications the 13.000-mhz oscillator is connected between the pxta l_in (amplifier input) and pxtal_out (amplified output). table 5-11 and table 5-12 list the 13.000-mhz specifications. to drive the 13.000-mhz crystal pins from an external source: 1. drive the pxtal_in pin with a digital signal with low and high levels as listed in table 5-12 . do not exceed vcc_pll or go below vss_pll by more than 100 mv. the minimum slew rate is 1 volt / 100 ns. the maximum current dr awn from the ex ternal clock source when the clock is at its maximum positive voltage typically is 1 ma. 2. float the pxtal_out pin or drive it in complement to the pxtal_in pin, with the same voltage level, slew rate, and input current restrictions. caution: the pxtal_in and pxtal_out pins must not be driven from an external source if the PXA270 processor sleep / deep sleep dc-dc converter is enabled. table 5-10. typical external 32.768-khz oscillator requirements symbol description min typical max units amplifier specifications vih_x input high voltage, txtal_in 0.99 1.10 1.21 v vil_x input low voltage, txtal_in ?0.10 0.00 0.10 v iin_xt input leakage, txtal_in ? ? 1 a cin_xt input capacitance, txtal_in/ txtal_out ? 18 25 pf ts_xt stabilization time ? ? 10 s board specifications rp_xt parasitic resistance, txtal_in/ txtal_out to any node 20 ? ? m ? cp_xt parasitic capacitance, txtal_in/ txtal_out, total ? ? 5 pf cop_xt parasitic shunt capacitance, txtal_in to txtal_out ? ? 0.4 pf table 5-11. typical 13.000-mhz crystal requirements parameter minimum typical maximum units frequency range 12.997 13.000 13.002 mhz frequency tolerance at 25 c ?50 ? +50 ppm oscillation mode ? fnd ? ? maximum change over temperature range ?50 ? +50 ppm drive level ? 10 100 uw load capacitance (c l )?10?pf maximum series resistance (r s )?50? ? aging per year, at operating temperature ? ? 5.0 ppm
5-12 electrical, mechanical, and thermal specification intel? PXA270 processor electrical specifications 5.6 clk_pio and clk_tout specifications clk_pio can be used to drive a buffered version of the pxtal_in oscillator input or can be used as a clock input alternative to pxtal_in. refer to table 5-13 for clk_pio specifications. a buffered and inverted version of the txtal_in oscillator output is driven out on clk_tout. refer to table 5-14 for clk_tout specifications. note: clk_tout and clk_pio are only available when software sets the oscc[pio_en] and oscc[tout_en] bits. table 5-12. typical external 13.000-mhz oscillator requirements symbol description min typical max units amplifier specifications vih_x input high voltage, pxtal_in 0.99 1.10 1.21 v vil_x input low voltage, pxtal_in ?0.10 0.00 0.10 v iin_xp input leakage, pxtal_in ? ? 10 a cin_xp input capacitance, pxtal_in/pxtal_out ? 40 50 pf ts_xp stabilization time ? ? 67.8 ms board specifications rp_xp parasitic resistance, pxtal_in/pxtal_out to any node 20 ? ? m ? cp_xp parasitic capacitance, pxtal_in/pxtal_out, total ? ? 5 pf cop_xp parasitic shunt capacitance, pxtal_in to pxtal_out ? ? 0.4 pf table 5-13. clk_pio specifications parameter specifications frequency 13 mhz frequency accuracy (derived from 13 mhz crystal) +/-200ppm symmetry/duty cycle variation 30/70 to 70/30% at vcc jitter +/-20ps max load capacitance (c l )50pf max rise and fall time (tr & tf) 15ns max with 50pf load table 5-14. clk_tout specifications parameter specifications frequency 32khz frequency accuracy (derived from 32 khz crystal) +/-200ppm symmetry/duty cycle variation 30/70 to 70/30% at vcc
electrical, mechanical, and thermal specification 5-13 intel? PXA270 processor electrical specifications 5.7 48 mhz output specifications software may configure gpio<11> or gpio<12> alternate functions to enable the 48-mhz clock output. the 48-mhz output clock is a divided-down output generated from the 312-mhz peripheral pll. refer to table 5-15 for the 48-mhz output specifications. refer to section 3 of this document for gpio alternate functions in the pin usage table. jitter +/-20ps max load capacitance (c l ) 50pf max rise and fall time (tr & tf) 15ns max with 50pf load table 5-14. clk_tout specifications parameter specifications table 5-15. 48 mhz output specifications parameter specifications frequency (derived from 13 mhz crystal) 48 mhz frequency accuracy (derived from 13 mhz crystal) +/-200ppm (maximum) symmetry/duty cycle variation 30/70 to 70/30% at vcc jitter +/-20ps max load capacitance (c l ) 50pf max rise and fall time (tr & tf) 15ns max with 50pf load
5-14 electrical, mechanical, and thermal specification intel? PXA270 processor electrical specifications
electrical, mechanical, and thermal specification 6-1 ac timing specifications 6 a pin?s alternating-current (ac) ch aracteristics include input and ou tput capacitance. these factors determine the loading for external drivers and other load analys es. the ac characteristics also include a derating factor, which indicates how mu ch the ac timings might vary with different loads. note: the timing diagrams in this chapter show bursts that start at 0 and proceed to 3 or 7. however, the least significant address (0) is not always received first during a burst tran sfer, because the intel? PXA270 processor requests the critical word first during burst accesses. table 6-1 shows the ac operating conditions for the high- and low-strength input, output, and i/o pins. all ac specification values are valid for the device?s entire temperature range. 6.1 ac test load specifications figure 6-1 represents the timing reference load used in defining the relevant timing parameters of the part. it is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. system designers use ibis or other simulation tools to correlate the timing refe rence load to system e nvironment. manufacturers correlate to their productio n test conditions (generally a coaxial transmission line terminated at the tester electronics). table 6-1. standard input, output, and i/o-pin ac operating conditions symbol description min typical max units c in input capacitance, all standard input and i/o pins ? ? 10 pf c out_h output capacitance, all standard high- strength output and i/o pins 20 ? 50 pf td f_h output derating, falling edge on all standard, high-strength output and i/o pins, from 50-pf load. ? tbd ? ns/pf td r_h output derating, rising edge on all standard, high-strength output and i/o pins, from 50-pf load. ? tbd ? ns/pf c out_l output capacitance, all standard low- strength output and i/o pins 20 ? 50 pf td f_l output derating, falling edge on all standard, low-strength output and i/o pins, from 50-pf load. ? tbd ? ns/pf td r_l output derating, rising edge on all standard, low-strength output and i/o pins, from 50-pf load. ? tbd ? ns/pf
6-2 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications 6.2 reset and power manager timing specifications the processor asserts the nreset_out pi n in one of several different modes: ? power-on reset ? hardware reset ? watchdog reset ? gpio reset ? sleep mode ? deep-sleep mode the following sections give the ti ming and specifications for entry into and exit from these modes. 6.2.1 power-on timing specifications power-on reset begins when a power supply is detected on the backup battery pin, vcc_batt, after the processor has been powered off. a power-on reset is equivalent to a hardware reset, in that all units are reset to the same known state as with a hardware reset. a power-on reset is a complete and total reset that occurs only at initial power on. the external power-supply system must enable the power supplies for the processor in a specific sequence to ensure proper operation. figure 6-2 shows the timing diagram for a power-on reset sequence. table 6-2 details the timing. the sequence for power-on reset is as follows: 1. vcc_batt is established, then nreset shou ld be de-asserted to initiate power-on reset. 2. pwr_out is asserted. the processor asserts nreset_out. 3. the external power-control subsystem de-ass erts nbatt_fault to signal that the main battery is connected and not discharged. 4. the processor asserts the sys_en signal to enable the power supplies vcc_io, vcc_mem, vcc_bb, vcc_usb, and vcc_lcd. vcc_usim can be established at this time also but can be independently controlled through its own control signals. vcc_io must be established first. the other supplies can turn on in any order, but they must all be established within 125 milliseconds of the assertion of sys_en. figure 6-1. ac test load i/o 50p f ? = 50?
electrical, mechanical, and thermal specification 6-3 intel? PXA270 processor ac timing specifications 5. the processor asserts the pwr_en signal to enable the power supplies vcc_core, vcc_sram, and vcc_pll. these supplies can turn on in any order but must all be established within 125 milliseconds of the assertion of pwr_en. 6. the external power-control subsystem de-asserts nvdd_fault to signal that all system power supplies have been properly established. 7. the processor de-asserts nreset_out and en ters run mode, executing code from the reset vector. note: nbatt_fault must be high before nreset is de-asserted. otherwise, the processor will not begin the power-on sequencing event. nvdd_fault is sampled only when the sys_del and pwr_del timers have expired. refer to the intel? pxa27x processor family developer?s manual , ?initial power on? an d ?deep-sleep exit states? for a state diagram. figure 6-2. power on reset timing table 6-2. power-on timing specificat ions (sheet 1 of 2)(oscc[cri] = 0) symbol description min typical max units t 1 delay from vcc_batt assertion to nreset de-assertion 10 ? ? ms t 2 delay from nreset de-assertion to sys_en assertion ? 10 1 ? ms t 3 delay from sys_en assertion to pwr_en assertion ? 125 ? ms t 4 power supply stabilization time (time to the deassertion of nvdd_fault after the assertion of pwr_en) ? ? 120 ms t 5 delay from the assertion of pwr_en to the de-assertion of nreset_out ? 125 ? ms t bramp vcc_batt power-on ramp rate ? 10 12 mv/us vcc_usb, vcc_io, vcc_mem, vcc_bb, vcc_lcd, vcc_usim vcc_core, vcc_sram, vcc_pll nbatt_fault nreset sys_en pwr_en nvdd_fault vcc_batt nreset_out t 1 t 3 t 5 t 2 t 4 t sysramp t bramp t pwrramp
6-4 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications 6.2.2 hardware reset timing the timing sequences shown in figure 6-3 for hardware reset and the specifications in table 6-3 and table 6-4 assume stable power supplies at the assertion of nreset. follow the timings indicated in section 6.2.1 if the power supplies are unstable. t sysramp power-on ramp rate for all external high -voltage power domains ? 10 12 mv/us t pwrramp power-on ramp rate for all external low -voltage power dom ains (including dynamic voltage changes on vcc_core) ? 10 12 mv/us notes: 1. if the oscc[cri] =1 then the delay from nreset de-assertion to sys_en assertion is 3000ms note: this long delay is attributed to the fact that when the cri bit is read as 1, (which indicates that the clk_req pin was floated during a hardware or powe r-on reset) the processor oscillator is supplied externally. this then forces the system to wait fo r the 32 khz oscillator and the 13 mhz oscillator to stabilize. table 6-2. power-on timing specifications (sheet 2 of 2)(oscc[cri] = 0) symbol description min typical max units figure 6-3. hard ware reset timing table 6-3. hardware reset timi ng specifications (oscc[cri] = 0) symbol description min typical max units t 6 delay between nreset asserted and nreset_out asserted ? < 100 ns 10 ms t 7 assertion time of nreset 6 ? ? ms t 8 delay between nreset de-asserted and nreset_out de-asserted 256 ? 265 ms nreset nreset_out t7 note: nbatt_fault and nvdd_fault must be deasserted during the reset sequence. t6 t8
electrical, mechanical, and thermal specification 6-5 intel? PXA270 processor ac timing specifications 6.2.3 watchdog reset timing watchdog reset is generated internally and therefore has no external pin dependencies. the nreset_out pin is the only indicator of watchdog reset; it stays asserted for t dhw_out . the timing is similar to that for gpio reset ? see figure 6-4 for details. 6.2.4 gpio reset timing gpio reset is generated externally, and the source is reconfigured as a standard gpio as soon as the reset propagates internally. the clocks module is not reset by gpio reset, so the timing varies based on the selected clock frequency. if the clocks and power manager is in a frequency-change sequence when gpio reset is asserted (see section 5.5.1, ?32.768-khz os cillator specifications? on page 5-9 .), then figure 6-4 shows the timing of gpio reset, and table 6-5 shows the gpio reset timing specifications. note: when bit gprod is set in the power manager ge neral configuration register, nreset_out is not asserted during gpio reset. for register de tails, see the ?clocks and power manager? chapter in the intel? pxa27x processor family developer?s manual . table 6-4. hardware reset timing specifications (oscc[cri] = 1) symbol description min typical max units t 6 delay between nreset asserted and nreset_out asserted ? < 100 ns 10 ms t 7 assertion time of nreset 6 ? ? ms t 8 delay between nreset de-asserted and nreset_out de-asserted 2256 ? 3265 ms figure 6-4. gpio reset timing gp[1] nreset_out ncs0 ta_gpio<1> tdhw_out_a tdhw_out tcs0
6-6 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications 6.2.5 sleep mode timing sleep mode is internally asserted, and it asserts the nreset_out and pwr_en signals. figure 6-5 and table 6-6 show the required timing parameters for sleep mode. note: when bit sl_rod is set in the power manager sleep configuration regi ster, nreset_out, is not asserted during gpio reset. see the ?clocks and power manager? chapter in the intel? pxa27x processor family developer?s manual for register details. table 6-5. gpio reset timing specifications symbol description min typical max units ta_gpio<1> minimum assert time of gpio<1> 1 in 13.000-mhz input clock cycles 4 4 ? ? cycles tdhw_out_a delay between gpio<1> asserted and nreset_out asserted in 13.000-mhz input clock cycles 6 4 ? 8 cycles tdhw_out delay between nreset_out asserted and nreset_out de-asserted, run or turbo mode 2 230 ? ? nsec tdhw_out_f delay between nreset_out asserted and nreset_out de-asserted, during frequency change sequence 3 5 ? 380 s tcs0 5 delay between nreset_out de- assertion and ncs0 assertion 1000 ? ? ns notes: 1. gpio<1> is not recognized as a reset source again until configured to do so in software. software must check the state of gpio<1> before configuring as a re set to ensure that no spurious reset is generated. for details, see the ?clocks and power manager? chapter in the intel? pxa27x processor family developer?s manual . 2. time is 512*n processor clock cycles plus up to 4 cycles of the 13.000-mhz input clock. 3. time during the frequency-change sequence depends on the st ate of the pll lock detector at the assertion of gpio reset. the lock detector has a ma ximum time of 350 s plus synchronization. 4. in standby, sleep, and deep-sleep modes, this time is in addition to the wake-up time from the low-power mode. 5. the tcs0 specification is also applicable to po wer-on reset, hardware reset, watchdog reset and deep- sleep/sleep mode exit.
electrical, mechanical, and thermal specification 6-7 intel? PXA270 processor ac timing specifications figure 6-5. sleep mode timing 6.2.6 deep-sleep mode timing deep-sleep mode is internally asserted, and it asserts the nreset_out and pwr_en signals. figure 6-6 and table 6-7 show the required timing parameters for sleep mode. the timing specifications listed are for software invoked (not battery or vdd fault) deep-sleep entry, unless specified. table 6-6. sleep-mode timing specifications symbol description min typical max 3 units t entry 5 delay between mcr sleep command issue to de-assertion of pwr_en 0.56 ? 2.5 1 msec t exit delay between wakeup event and run mode 0.50 ? 136.65 2,4 msec t pwrdelay delay between assertion of pwr_en to pll enable 2 0 ? 125 msec notes: 1. -1ms if not using dc2dc and -0.94ms if any internal sram banks are not powered 2. 0.15ms less time if exiting from sleep mode to 13m mode 3. add 0.1ms if the wake up event is external 4. oscillator start/cryst al stable times are programmable (300us-11ms) note: 6ms is user programmable using the oscc[osd] bi t. the remaining 5ms is an internal timer which counts until the oscillator is stabl e. (typical stabilization is 500 s. maximum can be upto 5ms) 5. nreset_out and nvdd_fault ar e programmable during sleep mode sys_en vcc_usb, vcc_io, vcc_bb,vcc_mem, vcc_lcd, vcc_usim pwr_en nvdd_fault vcc_core, vcc_sram, vcc_pll nreset_out (high) (enabled) wakeup event sleep (entry) sleep sleep (exit) normal intel? pxa27x state: tentry texit tpwrdelay
6-8 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications figure 6-6. deep-sleep-mode timing vcc_usb, vcc_io, vcc_bb, vcc_mem, vcc_lcd, vcc_usim vcc_core, vcc_sram, vcc_pll normal sys_en pwr_en nvdd_fault nreset_out wakeup event deep sleep (entry) deep sleep deep sleep (exit) intel? pxa27x state: tdentry tdexit tdpwr_delay deep-sleep command tdsys_delay tenable table 6-7. deep-sleep mode timing specifications symbol description min typical max 3 units t dentry 5 delay between deep-sleep command issue to de-assertion of sys_en 0.66 ? 1.66 1 msec t enable delay between de-assertion of pwr_en and sys_en ? 30 ? usec t dexit delay between wakeup event and run mode 0.60 ? 261.75 2,4 msec t dsysdelay delay between assertion of sys_en to pwr_en 2 0 ? 125 msec t dpwrdelay delay between assertion of pwr_en to pll enable 2 0 ? 125 msec note: timing specifications for nbatt_fault and/or nvdd_fault asserted deep-sleep mode entry are below: fault assert delay between nbatt_fault or nvdd_fault assertion (during all modes of operation including sleep mode) and deep-sleep mode entry 6 (the de-assertion of sys_en defines when the processor is in deep-sleep mode) 0.33 ? 1.56 msec notes: 1. -1ms if not using dc2dc 2. 0.15ms less time if exiting from deep-sleep mode to 13m mode 3. add 0.1ms if the wake up event is external 4. oscillator start/crystal stable times are programmable (300us-11ms) note: 6ms is user programmable using the oscc[osd] bi t. the remaining 5ms is an internal timer which counts until the oscillator is stabl e. (typical stabilization is 500 s. maximum can be upto 5ms) 5. nreset_out and nvdd_fault are programmable during sleep mode 6. assumes pmcr[bidae or vidae] bits are set to zero (default state) - the pmcr[bidae or vidae] bits are only read by the processor if nbat t_fault or nvdd_fault signals are asserted
electrical, mechanical, and thermal specification 6-9 intel? PXA270 processor ac timing specifications 6.2.6.1 gpio states in deep-sleep mode if the external high voltage power doma ins (vcc_io, vcc_mem, vcc_bb, vcc_lcd, vcc_usb, vcc_usim) remain powered on during deep-sleep, the pgsr values are driven onto all the gpio pins (that are configur ed as outputs) for a finite time period, then the pins default to the reset state (pu/pd) as describe d in chapter 2 of this manual. this sequence occurs for either software initiated or fault initiated deep-sleep entry. note: gpios<0,1,3,4,9,10> never float. they are powered from vcc_batt so wh en the system and the core power domains are removed (controlled by sys_en and pwr_en), the pu/pd resistors are still enabled due to vcc_batt remaining on. the delay between the initiation of deep-sleep mode and enabling the gpio pu /pd states, is system dependant because the processor is performing an unp redictable workload and requires an unknown amount of time to complete current processes. refer to the deep-sleep mode, ?clocks and power? section of the intel? pxa27x processor family developers manual for a description on deep-sleep mode entry sequence. table 6-8 shows the time period that the gpio pull-up/ pull-downs are enable d. listed below are the regulators and converter naming conventions: l1 = sleep/deep-sleep linear regulator l2 = high-current linear regulator dc2dc = sleep/deep-sleep dc-dc converter note: if the external high voltage power domains (vcc_io, vcc_mem, vcc_bb, vcc_lcd, vcc_usb, vcc_usim) are powered off during deep-sleep mode, the gpios behave the same as described above; however, they float after the supplies are removed. table 6-8. gpio pu/pd timing sp ecifications for deep-sleep mode description l2 l1 dc2dc units duration of the gpio pu/pd states being enabled and the de-assertion of pwr_en 0.1 0.13 1.13 msec
6-10 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications 6.2.7 standby-mode timing 6.2.8 idle-mode timing 6.2.9 frequency-change timing table 6-9. standby-mode timing specifications symbol description min typical max units ? 13m mode to standby mode entry ? 0.34 ? msec ? standby mode exit to 13m mode 1 0.28 ? 11.28 2 msec ? run mode to standby mode entry ? 0.34 ? msec ? standby mode exit to run mode 1 0.43 0.39 11.43 2 msec notes: 1. the 13m oscillator is programmable 2. add 0.1ms if the wake up event is external table 6-10. idle-mode timing specifications symbol description min typical max units ? 13m mode to deep idle mode entry ? 1 ? s ? deep idle mode exit to 13m mode ? 1 ? s ? run mode to idle run mode entry ? 1 ? s ? idle run mode exit to run mode ? 1 ? s table 6-11. frequency-change timing specifications symbol description min typical max units ? delay between mcr command to frequency change sequence completion ? 150 1 ? s ? delay to change between turbo, half- turbo and run modes ? 1 2 ? s ? delay to enter 13m mode from any run mode 3 ? 1 ? s ? delay to exit 13m mode to any run mode ? 2 4 ? s notes: 1. any change to the cccr[2n or l] bits followed by a write to clfcfg[f] to initiate a frequency change sequence, results in a pll restart 2. changing between turbo, half-turbo and run modes does not require a pll restart 3. software can only change into 13m mode from any run mode 4. assuming software uses the pll early enable feature (cccr[pll_early_en] prior to a frequency change sequence
electrical, mechanical, and thermal specification 6-11 intel? PXA270 processor ac timing specifications 6.2.10 voltage-change timing the pwr i 2 c uses the regular i 2 c protocol. the pwr i 2 c is clocked at 40 khz (160 khz fast- mode operation is supported). software controls the time required for initiating the voltage change sequence through completion. the voltage-change timing is a product of the number of commands issued plus the number of software programmed delays. table 6-12 shows the timing of a 1 byte command issued to the power manager ic. set the i 2 c programmable output ramp rate with a default/reset ramp rate of 10mv/ s (refer to vcc_core ramp rate specification in the electrical section ) to support vcc_core dynamic voltage management. table 6-12. voltage-change timing specification for a 1-byte command 6.3 gpio timing specifications table 6-13 shows the general-purpose i/o (gpio) ac timing specifications. symbol description min typical max units ? delay between voltage change sequence start 1 to command received by pmic ? 18 ? cycles 2 notes: 1. write 1 to pwrmode[vc] 2. 40 khz cycles table 6-13. gpio timing specifications symbol parameter min max units notes tagpio 1 assertion time required to detect gpio edge 154 ? ns run, idle, or sense power modes tagpiolp 2 assertion time required to detect gpio low-power edge 62.5 ? s standby, sleep, or deep-sleep power modes tdgpio 1 de-assertion time required to detect gpio edge 154 ? ns run, idle, or sense power modes tdgpiolp 2 de-assertion time required to detect gpio low-power edge 62.5 ? s standby, sleep, or deep-sleep power modes tdigpio 3 time it takes for a gpio edge to be detected internally 231 ? ns run, idle, or sense power modes tdigpiolp 4 time it takes for a gpio low- power edge to be detected internally 93.75 ? s standby, sleep, or deep-sleep power modes notes: 1. period equal to two 13-mhz cycles 2. period equal to two 32-khz cycles 3. period equal to three 13-mhz cycles 4. period equal to three 32-khz cycles note 4 describes the complete timing for a standby, sleep, or deep-sleep wake up source to be asserted and detected internally (2 cycles for assertion (note 2) and 1 additional cycle for detection).
6-12 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications 6.4 memory and expansion-ca rd timing specifications interfaces with the following memories must ob serve the ac timing requ irements given in the following subsections: ? section 6.4.1, ?internal sram re ad/write timing specifications? ? section 6.4.2, ?sdram parame ters and timing diagrams? ? section 6.4.3, ?rom parameters and timing diagrams? ? section 6.4.4, ?flash memory parameters and timing diagrams? ? section 6.4.5, ?sram parame ters and timing diagrams? ? section 6.4.6, ?variable-latency i/ o parameters and timing diagrams? ? section 6.4.7, ?expansion- card interface parameters and timing diagrams? note: the diagrams in this section use the following conventions: ? input signals to the processor are represented using dashed waveforms. ? outputs and bidirectional signals are represented using solid waveforms. ? fixed parameters are shown using double arrows in grey (black and white print) or green (color print). ? programmable parameters are shown using bold single arrows. ? the processor register that is used to change a specific timing is given in the corresponding timing table. 6.4.1 internal sram read/w rite timing specifications 6.4.2 sdram parameters and timing diagrams table 6-15 shows the timing parameters used in figure 6-7 . also see section 6.4.3 and figure 6-11 for additional sdram bus tenure information. see figure 6-10 for sdram fly-by bus tenures. table 6-14. sram read/write ac specification symbols parameters min typ max units tsramrd 4-beat read transfer ? 9 ? system bus clocks tsramwr 4-beat write transfer ? 7 ? system bus clocks
electrical, mechanical, and thermal specification 6-13 intel? PXA270 processor ac timing specifications table 6-15. sdram interface ac specifications (sheet 1 of 2) symbols parameters vcc_mem = 1.8v +20% / ?5% 3 vcc_mem = 2.5v +/- 10% 4 vcc_mem = 3.3v +/- 10% 5 units notes min typ max min typ max min typ max tsdclk sdclk1, sdclk2 period 9.6 ? 76.9 9.6 ? 76.9 9.6 ? 76.9 ns 1, 2 tsdcmd nsdcas, nsdras, nwe, nsdcs assert time 1 ?1 1 ?1 1 ?1 sdclk ? tsdcas nsdcas to nsdcas assert time 2 ?? 2 ?? 2 ?? sdclk ? tsdrcd nsdras to nsdcas assert time 1 mdcnfg [dtcx] 3 1 mdcnfg [dtcx] 3 1 mdcnfg [dtcx] 3 sdclk 6 tsdrp nsdras pre charge 2 mdcnfg [dtcx] 3 2 mdcnfg [dtcx] 3 2 mdcnfg [dtcx] 3 sdclk 6 tsdcl nsdras to nsdcas delay 2 mdcnfg [dtcx] 3 2 mdcnfg [dtcx] 3 2 mdcnfg [dtcx] 3 sdclk 6 tsdras nsdras active time 3 mdcnfg [dtcx] 7 3 mdcnfg [dtcx] 7 3 mdcnfg [dtcx] 7 sdclk 6 tsdrc nsdras cycle time 4 mdcnfg [dtcx] 11 4 mdcnfg [dtcx] 11 4 mdcnfg [dtcx] 11 sdclk 6 tsdwr write recovery time (time from last data in the precharge) 2 ?2 2 ?2 2 ?2 sdclk ? tsdsdos ma<24:10>, md<31:0>, dqm<3:0>, nsdcs<3:0>, nsdras, nsdcas, nwe, noe, sdcke1, rdnwr output setup time to sdclk<2:1> rise tbd ?? tbd ? tbd ?? ns ? tsdsdoh ma<24:10>, md<31:0>, dqm<3:0>, nsdcs<3:0>, nsdras, nsdcas, nwe, noe, sdcke1, rdnwr output hold time from sdclk<2:1> rise tbd ?? tbd ? tbd ?? ns ? vcc_core = 0.85 v +/? 10%, with 1.71 v<= vcc_mem <= 3.63 v vcc_core = 1.1 v +/? 10%, with 1.71 v <= vcc_mem <= 3.63 v vcc_core = 1.3 v +/? 10%, with 1.71 v <= vcc_mem <= 3.63 v
6-14 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications tsdsdis md<31:0> read data input setup time from sdclk<2:1> rise tbd ?? 0.5 ?? 0.5 ?? ns ? tsdsdih md<31:0> read data input hold time from sdclk<2:1> rise tbd ?? 1.8 ?? 1.8 ?? ns ? notes: 1. sdclk for sdram slowest period is accomplished by divide -by-2 of the 26-mhz clk_mem. the fastest possible sdclk is accomplished by configuring clk_mem at 104 mhz and not setting mdrefr[kxdb2]. 2. sdclk1 and sdclk2 frequencies are configured to be cl k_mem frequency divided by 1 or 2, depending on the bit fields mdrefr[k1db2] and mdrefr[k2db2] settings. 3. these numbers are for vcc_mem = 1.8 v +20% / ?5%, vol = 0.4 v , and voh = 1.4 v, with each applicable 4-bit field of the system memory buffer strength registers (bscntrp and bs cntrn) set to tbd (msb:lsb) and each applicable sdclk<2:1> divide-by-2 and divide-by -4 register bits mdrefr[kxdb2] clear. 4. these numbers are for vcc_mem = 2.5 v +/? 10%, vol = 0.4 v, and voh = 2.1 v, with each applicabl e 4-bit field of the system memory buffer strength registers (bscntrp and bscntrn) se t to 0b1010 (msb:lsb) and each appl icable sdclk<2:1> divide- by-2 and divide-by-4 register bit mdrefr[kxdb2] clear. 5. these numbers are for vcc_mem = 3.3 v +/? 10%, vol = 0.4 v, and voh = 2.4 v, with each applicabl e 4-bit field of the system memory buffer strength registers (bscntrp and bscntrn) se t to 0b1010 (msb:lsb) and each appl icable sdclk<2:1> divide- by-2 and divide-by-4 register bit mdrefr[kxdb2] clear. 6. refer to the ?memory controller? chapter in the intel? pxa27x processor family developer?s manual for register configuration. table 6-15. sdram interface ac specifications (sheet 2 of 2) symbols parameters vcc_mem = 1.8v +20% / ?5% 3 vcc_mem = 2.5v +/- 10% 4 vcc_mem = 3.3v +/- 10% 5 units notes min typ max min typ max min typ max
electrical, mechanical, and thermal specification 6-15 intel? PXA270 processor ac timing specifications figure 6-7. sdram timing nop act nop read nop pre nop act nop write nop pre nop 0b0000 0 1 2 3 tsdrcd tsdras tsdcmd tsdrp tsdrc tsdcmd tsdcl twr tsdsdoh tsdsdos tsdih tsdsdis tsdclk mask data values sdclk<1> sdcke<1> command nsdcs<0> nsdras nsdcas nwe md<31:0> read md<31:0> write dqm<3:0> rdnwr
6-16 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications figure 6-8. sdram 4-beat read/4-b eat write, different banks timing read(0) pre(1) nop act(1) nop write(1) nop col bank row col rd0_0 rd0_1 rd0_2 rd0_3 wd1_0 wd1_1 wd1_2 wd1_3 0b0000 0 1 2 3 1. mdcnfg[dtc] = 0b00 (cl = 2, trp = 2 clk, trcd = 1 clk), mdcnfg[stack] = 0b00 mask data bytes sdclk<1> sdcke<1> command nsdcs<0> nsdcs<1> nsdras nsdcas ma<24:10> nwe md<31:0> (read) md<31:0> (write) dqm<3:0> rdnwr 2. see the sdram timing diagram. notes:
electrical, mechanical, and thermal specification 6-17 intel? PXA270 processor ac timing specifications figure 6-9. sdram 4-beat write/4-beat write, same bank-same row timing nop write(0) nop write(0) nop col col wd0_0 wd0_1 wd0_2 wd0_3 wd0_4 wd0_5 wd0_6 wd0_7 mask0 mask1 mask2 mask3 mask4 mask5 mask6 mask7 mask data bytes 1. mdcnfg[dtc] = 0b01 (cl = 2, trp = 2 clks) sdclk<1> sdcke<1> command nsdcs<0> nsdras nsdcas ma<24:10> nwe md<31:0> dqm<3:0> rdnwr 2. see the sdram timing diagram. notes:
6-18 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications 6.4.3 rom parameters and timing diagrams table 6-16 lists the timings for rom reads. see figure 6-11 , figure 6-12 , figure 6-13 , and figure 6-14 for timings diagrams representing burst and non-burst rom reads. note: table 6-16 lists programmable register items. see the ?memory controller? chapter in the intel? pxa27x processor family developer?s manual for register configurations for more information on these items. figure 6-10. sdram fly-by dma timing read pre nop act nop write nop col bank row col rd0 rd1 rd2 rd3 wd0 wd1 wd2 wd3 0b0000 mask0 mask1 mask2 mask3 drive data wd3 drive data wd2 drive data wd1 drive data wd0 latch dval[1] asserted latch data rd3 latch data rd2 latch data rd1 latch data rd0 1. mdcnfg[dtc] = 0b00 (cl = 2, trp = 2 clk, trcd = 1 clk) mask data bytes latch data on rising edge of sdclk<1> when dval<0> is asserted. using dval<1> driven two clocks early, drive data on rising edge of sdclk<2>. sdclk<1> sdclk<2> sdcke<1> command nsdcs<0> nsdcs<2> nsdras nsdcas ma<24:10> nwe md<31:0> dqm<3:0> rdnwr dval<0> dval<1> 2. see the sdram timing diagram. notes: table 6-16. rom ac specification (sheet 1 of 2) symbols parameters min typ max units ? notes tromas address setup to ncs assert 1 ? 1 clk_mem ? tromces ncs setup to noe asserted ? ? 0 clk_mem ? tromceh ncs hold from noe deasserted ? ? 0 clk_mem ? tromdsoh md setup to address valid 1.5 ? ? clk_mem ?
electrical, mechanical, and thermal specification 6-19 intel? PXA270 processor ac timing specifications tromdoh md hold from address valid 0 ? ? clk_mem ? tromavdvf address valid to data valid for the first read access 2 mscx[rdf]+2 32 clk_mem ? tromavdvs address valid to data valid for subsequent reads of non-burst devices 1 mscx[rdf]+1 31 clk_mem ? tflashavdvs address valid to data valid for subsequent reads of burst devices 1 mscx[rdn]+1 31 clk_mem ? tromcd ncs deasserted after a read of next ncs or nsdcs asserted (minimum) 1 mscx[rrr]*2+ 1 15 clk_mem ? ? numbers shown as integer multiples of the clk_mem period are ideal. actual numbers vary with pin-to-pin differences in loading and transition direction (rise or fall). for more in formation, refer to the ?memory control? chapter in the intel? pxa27x processor family developer?s manual . table 6-16. rom ac specification (sheet 2 of 2) symbols parameters min typ max units ? notes
6-20 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications figure 6-11. 32-bit non-burst rom, sram, or flash read timing 0 1 2 3 0b00 0b00 / 0b01 / 0b10 / 0b11 0b00 corresponding mask value tromcd tromavdvs tromavdvs tromavdvs tromavdvf tromas tromdoh tromdsoh tromdoh tromdsoh tromdoh tromdsoh tromdoh tromdsoh tromceh tromces note: msc0[rdf0] = 4, msc0[rrr0] = 1 clk_mem ncs<0> ma<25:2> ma<1:0>(sa1110x='0') ma<1:0>(sa1110x='1') nadv(nsdcas) noe nwe rdnwr md<31:0> dqm<3:0>(sa1110x='0') dqm<3:0>(sa1110x='1') ncsx or nsdcsx
electrical, mechanical, and thermal specification 6-21 intel? PXA270 processor ac timing specifications figure 6-12. 32-bit burst-of-eight rom or flash read timing 0 1 2 3 4 5 6 7 0b00 0b00 / 0b01 / 0b10 / 0b11 0b0000 corresponding mask value tromcd tromavdvs tromavdvf tdoh tdsoh tceh tces tas note: msc0[rdf0] = 4, msc0[rdn0] = 1, msc0[rrr0] = 1 clk_mem ncs<0> ma<25:5> ma<4:2> ma<1:0>(sa1110x='0') ma<1:0>(sa1110x='1') nadv(nsdcas) noe nwe rdnwr md<31:0> dqm<3:0>(sa1110x='0') dqm<3:0>(sa1110x='1') ncsx or nsdcsx
6-22 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications figure 6-13. eight-beat burst read from 16-bit burst-of-four rom or flash timing address 0 1 2 3 0 1 2 3 0b0 0b0 / 0b1 0b00 0b00 or 0b10/0b01 tromcd tromavdvs tromavdvf tromavdvs tromavdvf tromdoh tromdsoh tromdoh tromdsoh tromceh tromces tromas note: msc0[rdf0] = 4, msc0[rdn0] = 1, msc0[rrr0] = 0 clk_mem ncs<0> ma<25:4> ma<3> ma<2:1> ma<0>(sa1110x='0') ma<0>(sa1110x='1') nadv(nsdcas) noe nwe rdnwr md<15:0> dqm<1:0>(sa1110x='0') dqm<1:0>(sa1110x='1') ncsx or nsdcsx
electrical, mechanical, and thermal specification 6-23 intel? PXA270 processor ac timing specifications 6.4.4 flash memory param eters and timing diagrams the following sections describe the read/write parameters and timing diagrams for asynchronous and synchronous flash-memory interf aces with the memory controller. 6.4.4.1 flash memory read pa rameters and timing diagrams section 6.4.4.1.1 describes asynchronous flash reads. section 6.4.4.1.2 describes synchronous flash reads. 6.4.4.1.1 asynchronous flash read parameters and timing diagrams the timings listed in table 6-16 for rom reads also apply to asynchronous flash reads. see figure 6-11 , figure 6-12 , figure 6-13 , and figure 6-14 for timings diagrams representative of an asynchronous flash read. figure 6-14. 16-bit rom/flash/sram read for 4/2/1 bytes timing addr addr + 1 addr addr addr addr + 1 0 0 0 0 0/1 0/1 0/1 0/1 0b00 0b00 0b00 0b00 mask mask mask mask tflashavdvs tromavdvf tromavdvf tromavdvf tromavdvs tromavdvf tromcd tromcd tromcd tromdoh tromdsoh tromdoh tromdsoh tromdoh tromdsoh tromdoh tromdsoh tromdoh tromdsoh tromdoh tromdsoh tromces tromces tromces tromceh tromces tromas tromas tromas tromas 32-bit read note: msc0[rdf0] = 2, msc0[rdn0] = 1, msc0[rrr0] = 1 16-bit read 8-bit read applies to: 16-bit rom or non-burst flash 16-bit sram applies to: 16-bit rom or non-burst flash 16-bit sram 16-bit burst flash applies to: 16-bit rom or non-burst flash 16-bit sram 16-bit burst flash 32-bit read applies to: 16-bit burst flash clk_mem ncs<0> ma<25:1> ma<0>(sa1110x='0') ma<0>(sa1110x='1') nadv(nsdcas) noe nwe rdnwr md<15:0> dqm<1:0>(sa1110x='0') dqm<1:0>(sa1110x='1')
6-24 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications 6.4.4.1.2 synchronous flash read parameters and timing diagrams table 6-17 lists the timing parameters used in figure 6-15 , and, for stacked flash packages, figure 6-16 . table 6-17. synchronous flash read ac specifications (sheet 1 of 2) symbols parameters min typ max min typ max min typ max units notes divide by 1 2 divide by 2 3 divide by 4 4 tffclk sdclk0 period 9.6 ? 38.5 19. 2 ? 76.9 38.5 ? 154 ns 1 tffas ma<25:0> setup to nsdcas (as nadv) asserted 1 ? 1 1 ? 2 1 ? 4 clk_mem ? tffces ncs setup to nsdcas (as nadv) asserted 1 ? 1 1 ? 2 1 ? 4 clk_mem ? tffadv nsdcas (as nadv) pulse width 1 ? 1 3 ? 3 7 ? 7 clk_mem ? tffos nsdcas (as nadv) deassertion to noe assertion 1 fcc ? 1 (for fcc<5) fcc ? 2 (for fcc>=5) 13 2 (fcc ? 1) * 2 (for fcc<5) (fcc ? 2) * 2 (for fcc>=5) 26 7 (fcc * 4) ? 7 (for fcc<5) (fcc ? 2) * 4 (for fcc>=5) 52 clk_mem 5 tffceh noe deassertion to ncs deassertion 4 ? 4 8 ? 8 16 ? 16 clk_mem ? tffds clk to data valid 2 fcc 15 2 fcc 15 2 fcc 15 clk_mem 5 vcc_mem = 1.8v +20% / -5% 6 vcc_mem = 2.5v +/- 10% 7 vcc_mem = 3.3v +/- 10% 8 tffsdos ma<25:0>, md<31:0>, dqm<3:0>, ncs<3:0>, nsdcas (nadv), nwe, noe, rdnwr output setup time to sdclk<2:1> rise tbd ? ? tb d ? ? tbd ? ? ns ? tffsdoh ma<25:0>, md<31:0>, dqm<3:0>, ncs<3:0>, nsdcas (nadv), nwe, noe, rdnwr output hold time from sdclk<2:1> rise tbd ? ? tb d ? ? tbd ? ? ns ? vcc_core = 0.85 v +/ ? 10%, with 1.71 v<= vcc_mem <= 3.63 v vcc_core = 1.1 v +/? 10%, with 1.71 v <= vcc_mem <= 3.63 v vcc_core = 1.3 v +/? 10%, with 1.71 v <= vcc_mem <= 3.63 v
electrical, mechanical, and thermal specification 6-25 intel? PXA270 processor ac timing specifications tffsdis md<31:0> read data input setup time from sdclk<2:0> rise tbd ? ? 0.5 ? ? 0.5 ? ? ns ? tffsdih md<31:0> read data input hold time from sdclk<2:0> rise tbd ? ? 1.8 ? ? 1.8 ? ? ns ? notes: 1. sdclk0 may be configured to be clk_mem divided by 1, 2 or 4. sdclk0 for synchronous flash memory can be at the slowest, divide-by-4 of the 26-mhz clk_mem. the fastest possible sdcl k0 is accomplished by confi guring clk_mem at 104 mhz and clearing the mdrefr[k0db2] or mdrefr[k0db4] bit fields. 2. sdclk0 frequency equals clk_mem frequency (mdrefr[k0d b4] and mdrefr[k0db2] bit fields are clear) 3. sdclk0 frequency equals clk_mem/2 frequency (mdrefr[k0db2] is set and mdrefr[k0db4] is clear). 4. sdclk0 frequency equals clk_mem/4 frequency (mdrefr[k0db4] is set). 5. use sxcnfg[sxclx] to configure the value for the frequency configuration code (fcc). 6. these numbers are for vcc_mem = 1.8 v +20% / -5%, vol = 0.4 v, and voh = 1.4 v, with each applicable 4-bit field of the system memory buffer strength registers (bscn trp and bscn trn) set to tbd (msb:lsb) and each applicable sdclk0 divide- by-2 and divide-by-4 register bits (mdrefr[k0db2] and mdre fr[k0db4]) clear. if mdrefr[k0db2 is set, the corresponding output setup and hold times are increased and decreas ed, respectively, by 0.25 times the sdclk0 period. 7. these numbers are for vcc_mem = 2.5 v +/? 10%, vol = 0.4 v, and voh = 2.1 v, with each applicabl e 4-bit field of the system memory buffer strength registers (bscntrp and bscntrn) se t to 0b1010 (msb:lsb) and each appl icable sdclk0 divide-by-2 and divide-by-4 register bit (mdrefr[k0db2] and mdrefr[k0db4 ]) clear. if mdrefr[k0db2 is set, the corresponding output setup and hold times are increased and decreased, re spectively, by 0.25 times the sdclk0 period. 8. these numbers are for vcc_mem = 3.3 v +/? 10%, vol = 0.4 v, and voh = 2.4 v, with each applicabl e 4-bit field of the system memory buffer strength registers (bscntrp and bscntrn) se t to 0b1010 (msb:lsb) and each appl icable sdclk0 divide-by-2 and divide-by-4 register bit (mdrefr[k0db2] and mdrefr[k0db4 ]) clear. if mdrefr[k0db2 is set, the corresponding output setup and hold times are increased and decreased, re spectively, by 0.25 times the sdclk0 period. table 6-17. synchronous flash read ac specifications (sheet 2 of 2) symbols parameters min typ max min typ max min typ max units notes
6-26 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications figure 6-15. synchronous flash burst-of-eight read timing 0b00 0b00/0b01/0b10/0b11 0b0000 corresponding mask value code+1 code notes: 1) sxcnfg[cl] = 0b100 (cl = 5, frequency code configuration = 4) 2) code = frequency configuration code clk_mem sdclk<0> ma<19:2> ma<1:0>(sa1110x=0) ma<1:0>(sa1110x=1) ncs<0> nadv(nsdcas) noe nwe md<31:0> dqm<3:0>(sa1110x=0) dqm<3:0>(sa1110x=1)
electrical, mechanical, and thermal specification 6-27 intel? PXA270 processor ac timing specifications figure 6-16. synchronous flash stacked burst-of-eight read timing 0b00 0b00/0b01/0b10/0b11 0b0000 corresponding mask value code+1 code note: sxcnfg[cl] = 0b100 (cl = 5, frequency code configuration = 4) sa1110cr[sxstack] = 0b01 clk_mem sdclk<3> ma<19:2> ma<1:0>(sa1110x=0) ma<1:0>(sa1110x=1) ncs<0> nadv(nsdcas) noe nwe md<31:0> dqm<3:0>(sa1110x=0) dqm<3:0>(sa1110x=1)
6-28 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications figure 6-17 indicates which clock data would be latched following the assertion of nsdcas(adv), depending on the configuration of the sxcnfg[sxclx] bit field. the period in the diagram indicated by differen t frequency configuration codes (f codes or fccs) is equal to the number of sdclk0 cycles between the read command and the clock edge on which data is driven onto the bus. figure 6-17. first-access la tency configuration timing valid address 0b0000 beat 0 beat 1 beat 2 beat 3 beat 4 beat 5 beat 0 beat 1 beat 2 beat 3 beat 4 beat 0 beat 1 beat 2 beat 3 beat 0 beat 1 beat 2 beat 0 beat 1 beat 0 code 7 code 6 code 5 code 4 code 3 code 2 note: code = frequenc y configuration code sdclk<0> ncs<0> ma<19:0> nsdcas dqm<3:0> md (code = 2) md (code = 3) md (code = 4) md (code = 5) md (code = 6) md (code = 7)
electrical, mechanical, and thermal specification 6-29 intel? PXA270 processor ac timing specifications the burst read ex ample shown in figure 6-18 represents waveforms that result when sxcnfg[sxclx] is configured as 0b0100, representing a frequency configuration code equal to 3. the following example can be used to help determine the appropriate setting for sxcnfg[sxclx]. parameters defined by the processor: ? tffsdoh (max) = sdclk<0> to ce# (nce), adv# (nadv), or address valid, whichever occurs last ? tffsdis (min) = data setup to sdclk<0> parameters defined by flash memory: ? tvlqv (min) = adv# low to output delay ? tvlch (min) = adv# low to clock ? tchqv (max) = sdclk<0> to output valid use the following equations when calculating the frequency configuration code: (1) sdclk period = (1 / frequency) (2) n (sdclk period) tvlqv - tvlch - tchqv (3) n = (tvlqv - tvlch - tchqv) / sdclk period, where n = frequency configuration code rounded up to integer value (4) sdclk period tchqv + tffsdis example the timing information below is only an example. see table 6-17 for actual synchronous ac timings. sdclk<0> frequency = 50 mhz tvlqv = 70 ns (typical timing from synchronous flash memory) tvlch = 10 ns (min) tchqv = 14 ns (min) from eq.(1): 1 / 50 (mhz) = 20 ns from eq.(2): n(20 ns) 70 ns - 10 ns - 14 ns n(20 ns) 46 ns n = (46 / 20) ns = 2.3 ns n = 3 use equation 4 to help verify the maximum poss ible frequency at which the synchronous flash memory can run with the memory controller. the following example uses equation 4: sdclk<0> frequency = 66 mhz tchqv = 11 ns (max) tffsdis = 3 ns (min) from eq. (1): 1 / 66 (mhz) = 15.15 ns from eq. (4): 15.15 ns 11 ns + 3 ns 15.15 ns 14 ns the results from this example indicate that the 66-mhz memory works without problems with the memory controller. note: all ac timings must be considered to avoid timing violations in the memory-to-memory-controller interface.
6-30 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications 6.4.4.2 flash memory write pa rameters and timing diagrams table 6-18 lists the ac specification for both burs t and non-burst flash writes shown in figure 6-19 and, for stacked flash packages , figure 6-20 . figure 6-18. synchronous flash burst read example valid address beat 0 beat1 tchqv tffsdoh tffsdoh tffsdoh tffsdis tvlqv tavch sdclk<0> ncs<0> nsdcas (adv#) ma md table 6-18. flash memory ac specification (sheet 1 of 2) symbols parameters min typ max units 1 notes tflashas address setup to ncs assert 1 ? 1 clk_mem ? tflashah address hold from nwe de-asserted 1 ? 1 clk_mem ? tflashasw address setup to nwe asserted 1 ? 3 clk_mem 2 tflashces ncs setup to nwe asserted 2 ? 2 clk_mem ? tflashceh ncs hold from nwe de-asserted 1 ? 1 clk_mem ? tflashwl nwe asserted time 1 mscx[rdf]+1 31 clk_mem ? tflashdswh md/dqm setup to nwe de-asserted 2 mscx[rdf]+2 32 clk_mem ? tflashdh md/dqm hold from nwe de- asserted 1 ? 1 clk_mem ? tflashdsoh md setup to address valid 1.5 ? ? clk_mem ?
electrical, mechanical, and thermal specification 6-31 intel? PXA270 processor ac timing specifications tflashdoh md hold from address valid 0 ? ? clk_mem ? tflashcd ncs de-asserted after a read/write to next ncs or nsdcs asserted (minimum) 1 mscx[rrr]*2 + 1 15 clk_mem ? notes: 1. numbers shown as integer multiples of the clk_mem period are ideal. actual numbers vary with pin-to-pin differences in loading and transition direction (rise or fall). 2. on the first data beat of burst transfer, the tflashasw is 3 clk_mem periods. on subsequent data beats, the tflashasw is 1 clk_mem period. figure 6-19. 32-bit flash write timing table 6-18. flash memory ac specification (sheet 2 of 2) symbols parameters min typ max units 1 notes command address data address 0b00 0b00 cmd data 0b0000 0b0000 tflashcd tflashdswh tflashdswh tflashwl tflashwl tflashcd tflashdh tflashdh tflashah tflashceh tflashces tflashasw tflashah tflashceh tflashces tflashasw tflashas tflashas note: msc0[rdf0] = 2, msc0[rrr0] = 2 first bus cycle second bus cycle clk_mem ncs<0> ma<25:2> ma<1:0> nwe noe rdnwr md<31:0> dqm<3:0> nadv(nsdcas) ncsx or nsdcsx
6-32 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications figure 6-20. 32-bit stacked flash write timing command address data address 0b00 0b00 cmd data 0b0000 0b0000 tflashcd tflashdswh tflashdswh tflashwl tflashwl tflashcd tflashdh tflashdh tflashah tflashceh tflashces tflashasw tflashah tflashceh tflashces tflashasw tflashas tflashas * msc0[rdf0] = 2, msc0[rrr0] = 2, sa1110{sxstack] = 00 first bus cycle second bus cycle clk_mem nwe ma<25:2> ma<1:0> ncs<0> or ncs<1> noe rdnwr md<31:0> dqm<3:0> nadv(nsdcas) ncsx
electrical, mechanical, and thermal specification 6-33 intel? PXA270 processor ac timing specifications 6.4.5 sram parameters and timing diagrams the following sections describe the read/write parameters and timing diagrams for sram interfaces with the memory controller. 6.4.5.1 sram read parame ters and timing diagrams the timing for a read access is identical to that for a non-burst rom read (see figure 6-11 ). the timings listed in table 6-16 for rom reads are also used for sram reads. see figure 6-11 and figure 6-14 for timings diagrams representing 16-bit sram transferring four, two, and one byte(s) during read-bus tenures. 6.4.5.2 sram write parame ters and timing diagrams figure 6-22 and figure 6-23 show the timing for 32-bit and 16-bit sram writes. table 6-19 lists the timings used in figure 6-22 and figure 6-23 . figure 6-21. 16-bit flash write timing addr 0b0 bytes 1:0 0b00 tflashcd tflashdswh tflashwl tflashdh tflashceh tflashces tflashas applies to: 16-bit non-burst flash 16-bit burst flash note: msc1[rdn2] = 2, msc1[rdf2] = 1, msc1[rrr2] = 2 clk_mem ncs<2> ma<25:1> ma<0> nwe noe rdnwr md<15:0> dqm<1:0> nadv(nsdcas) ncsx or nsdcsx
6-34 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications during writes, data pins are actively driven by the processor and are not three-stated, regardless of the states of the indivi dual dqm signals. for sram writes, the dqm signals are used as byte enables. note: table 6-19 lists programmable register items. see the ?memory controller?chapter in the intel? pxa27x processor family developer?s manual for register configurations for more information on these items. table 6-19. sram write ac specification symbols parameters min typ max units 1 notes tsramas address setup to ncs assert 1 ? 1 clk_mem ? tsramah address hold from nwe de-asserted 1 ? 1 clk_mem ? tsramasw address setup to nwe asserted 1 ? 3 clk_mem 2 tsramces ncs setup to nwe asserted 2 ? 2 clk_mem ? tsramceh ncs hold from nwe de-asserted 1 ? 1 clk_mem ? tsramwl nwe asserted time 1 mscx[rdn]+1 31 clk_mem ? tsramdswh md/dqm setup to nwe de-asserted 2 mscx[rdn]+2 32 clk_mem ? tsramdh md/dqm hold from nwe de- asserted 1 ? 1 clk_mem ? tramcd ncs de-asserted after a read to next ncs or nsdcs asserted (minimum) 1 mscx[rrr]*2+ 1 15 clk_mem ? notes: 1. numbers shown as integer multiples of the clk_mem period ar e ideal. actual numbers vary with pin-to-pin differences in loading and transition dire ction (rise or fall). 2. on the first data beat of burst transfer, the tsramasw is 3 clk_mem periods. on subsequent data beats, the tsramasw is 1 clk_mem period.
electrical, mechanical, and thermal specification 6-35 intel? PXA270 processor ac timing specifications figure 6-22. 32-bit sram write timing 0 1 2 3 byte addr byte addr byte addr byte addr d0 d1 d2 d3 mask0 mask1 mask2 mask3 tsramcd tsramwl tsramwl tsramwl tsramwl tsramdoh tsramdh tsramdswh tsramcehw tsramah tsramasw tsramah tsramasw tsramcesw tsramas note: 4-beat burst, msc0[rdn0] = 2, msc0[rrr0] = 1 clk_mem ncs<0> ma<25:2> ma<1:0> nwe noe rdnwr md<31:0> dqm<3:0> ncsx or nsdcsx nadv(nsdcas)
6-36 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications 6.4.6 variable-latency i/o parameters and timing diagrams the following sections describe the read/write parameters and timing diagrams for vlio memory interfaces with the memory controller. table 6-20 lists the timing-information references for both the read and the write timing diagrams. note: table 6-20 lists programmable register items. for more informa tion on these items, see the ?memory controller? chapter in the intel? pxa27x processor family developer?s manual for register configurations. figure 6-23. 16-bit sram write for 4/2/1 byte(s) timing addr addr+1 addr addr '0' '0' '0' '0' or '1' bytes 1:0 bytes 3:2 bytes 1:0 byte 0 or 1 0b00 0b00 0b01 / 0b10 tsramcd tsramdswh tsramdswh tsramdswh tsramwl tsramwl tsramwl tsramwl tsramcd tsramcd tsramdh tsramdh tsramdswh tsramdh tsramdh tsramceh tsramces tsramceh tsramces tsramceh tsramwl tsramasw tsramah tsramces tramas tramas tramas 32-bit write 16-bit write 8-bit write note: msc1[rdf2]=1, msc1[rdn]=2, msc1[rrr2]=2 clk_mem ncs<2> ma<25:1> ma<0> nwe noe rdnwr md<15:0> dqm<1:0> nadv(nsdcas) n csx or nsdcsx
electrical, mechanical, and thermal specification 6-37 intel? PXA270 processor ac timing specifications 6.4.6.1 variable latency i/o read timing figure 6-24 shows the timing for 32-bit variable -latency i/o (vlio) memory reads. table 6-20 lists the timing parameters used in these diagrams. table 6-20. vlio timing symbols parameters min typ max 2 units 1 notes tvlioas address setup to ncs asserted 1 ? 1 clk_mem ? tvlioah address hold from npwe/noe de- asserted 2 mscx[rdn] 30 clk_mem ? tvlioasrw0 address setup to npwe/noe asserted (1st access) 3 ? 3 clk_mem ? tvlioasrwn address setup to npwe/noe asserted (next access(es)) 2 mscx[rdn] 30 clk_mem ? tvlioces ncs setup to npwe/noe asserted 2 ? 2 clk_mem ? tvlioceh ncs hold from npwe/noe de- asserted 1 ? 1 clk_mem ? tvliodswh md/dqm setup (minimum) to npwe de-asserted 5 mscx[rdf]+2 32 clk_mem ? tvliodh md/dqm hold from npwe de- asserted 1 ? 1 clk_mem ? tvliodsoh md setup to address changing 1.5 ? clk_mem ? tvliodoh md hold from address changing 0 ? ns ? tvliordyh rdy hold from npwe/noe de- asserted 0 ? ? ns ? tvliorwa npwe/noe assert period between writes 4 msc[rdf]+1 + waits 31 + waits clk_mem ? tvliorwd npwe/noe de-asserted period between writes 4 mscx[rdn*2] 60 clk_mem 3 tvliocd ncs de-asserted after a read/write to next ncs or nsdcs asserted (minimum) 1 mscx[rrr]*2 + 1 15 clk_mem ? notes: 1. numbers shown as integer multiples of the clk_mem period are ideal. actual numbers vary with pin-to-pin differences in loading and transition direction (rise or fall). 2. maximum values reflect th e register dynamic ranges. 3. depending on the programmed value of msc[rdn] and the cl k_mem speed, this can be a significant amount of time. processor does not drive the data bus during this time between transfers. if the vlio does not drive the data bus during this time between transfers, the data bus is not driven for this period of time. if msc[ rdn] is programmed to 60 (which equals 60 clk_mem cycles), then the data bus could potentia lly not be driven for 30*2 = 60 clk_mem cycles.
6-38 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications 6.4.6.2 variable-late ncy i/o write timing figure 6-25 shows the timing for 32-bit vlio memory writes. table 6-20 list the timing parameters used in figure 6-25 . figure 6-24. 32-bit vlio read timing addr addr + 1 addr + 2 addr + 3 0b00 0b00/0b01/0b10/0b11 0b0000 corresponding mask value tvliocd tvliorwa tvliorwd tvliorwa tvliorwd tvliorwa tvliorwd tvliodoh tvliodsoh tvliodoh tvliodsoh tvliodoh tvliodsoh tvliodoh tvliodsoh tvliordyh tvliordyh tvliordyh tvliordyh tvlioceh tvlioah tvlioasrwn tvlioah tvlioasrwn tvlioah tvlioasrwn tvlioah tvlioasrw0 tvlioces tvlioas 0 waits 1 wait 2 waits 3 waits note: msc0[rdf0] = 3, msc0[rdn0 = 2, msc0[rrr0] = 1 clk_mem ncs<0> ma<25:2> ma<1:0>(sa1110x='0') ma<1:0>(sa1110x='1') noe npwe rdnwr rdy rdy_sync md<31:0> dqm<3:0>(sa1110x='0') dqm<3:0>(sa1110x='1') ncsx or nsdcsx
electrical, mechanical, and thermal specification 6-39 intel? PXA270 processor ac timing specifications figure 6-25. 32-bit vlio write timing addr addr + 1 addr + 2 addr + 3 0b00 d0 d1 d2 d3 mask0 mask1 mask2 mask3 tvliocd tvliorwa tvliorwd tvliorwa tvliorwd tvliorwa tvliorwd tvliorwa tvliodh tvliodh tvliodswh tvliodh tvliodswh tvliodh tvliodswh tvliodswh tvliordyh tvliordyh tvliordyh tvliordyh tvlioceh tvlioah tvlioasrwn tvlioah tvlioasrwn tvlioah tvlioasrwn tvlioah tvlioasrw0 tvlioces tvlioas 0 waits note: msc0[rdf0] = 3, msc0[rdn0] = 2, msc0[rrr0] = 1 1 wait 2 waits 3 waits clk_mem ncs<0> ma<25:2> ma<1:0> npwe noe rdnwr rdy rdy_sync md<31:0> dqm<3:0> ncsx or nsdcsx
6-40 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications 6.4.7 expansion-card interface parameters and timing diagrams the following sections describe the read/write parameters and timing diagrams for compactflash* and pc card* (expansion card) memory in terfaces with the memory controller. table 6-21 shows the timing parameters used in the timing diagrams, figure 6-26 and figure 6-27 . note: table 6-21 lists programmable register items. see the ?memory controller? chapter in the intel? pxa27x processor family developer?s manual for register configurations for more information on these items. table 6-21. expansion-card interface ac specifications symbols parameters min typ max units notes tcdavcl address valid to cmd low 2 mcx[set] 127 clk_mem 1,2,3,4 tcdchai cmd high to address invalid 0 mcx[hold] 63 clk_mem 1,2,3,5 tcddvcl write data valid to cmd low ? 1 ? clk_mem 1,3 tcdchwdi cmd high to write data invalid ? 4 ? clk_mem 1,3 tcddvch read data valid to cmd high 2 ? ? clk_mem 1,3 tcdchrdi cmd high to read data invalid 0 ? ? ns 3 tcdcmd cmd assert during transfers ? tcdclps + tcdphch + npwait assertion ? clk_mem 1,3 tcdilcl niois16 low to cmd low 4 ? ? clk_mem 1,3 tcdchih cmd high to niois16 high 2 ? ? clk_mem 1,3 tcdclps cmd low to npwait sample ? x_asst_wait ? clk_mem 1,3,6,7 tcdphch npwait high to cmd high ? x_asst_hold ? clk_mem 1,3,6,8 notes: 1. all numbers shown are ideal, integer multiples of the clk_mem pe riod. actual numbers vary with pin-to-pin differences in loading and transition direct ion (rise or fall). 2. includes signals ma[25:0], npreg, and npsktsel. 3. cmd refers to signals npwe , npoe, npiow, and npior 4. refer to the intel? pxa27x processor family developer?s manual , expansion memory timing c onfiguration registers to change the assertion of cmd using the mcx[set] bit fields. 5. refer to the intel? pxa27x processor family developer?s manual , expansion memory timing c onfiguration registers to increase the assertion of cmd using the mcx[hold] bit fields. 6. refer to the intel? pxa27x processor family developer?s manual , expansion memory timing c onfiguration registers to increase timings. the timings are changed by programming the mcx[asst] respec tive bit fields. refer to the pc card interface command assertion code table to see the effect of mcx[asst]. 7. tcdclps equals clk_mem * x_asst_wait. refer to the pc card interface command assertion code table in the intel? pxa27x processor family developer?s manual for the correlation between x_asst_wait and the mcx[asst] bit field. 8. tcdphch equals clk_mem * x_asst_hold. refer to the pc card interface command assertion code table in the intel? pxa27x processor family developer?s manual for the correlation between x_asst_hold and the mcx[asst] bit field.
electrical, mechanical, and thermal specification 6-41 intel? PXA270 processor ac timing specifications figure 6-26. expansion-card memory or i/o 16-bit access timing read data latch tcdcmd tcdphch tcdclps tcdavcl tcdchai tcdchrdi tcddvch tcdchwdi tcddvcl tcdchih tcdilcl clk_mem npce[2],npce[1] ma[25:0],npreg,psktsel npwe,npoe,npiow,npior niois16 md[15:0] (write) rdnwr npwait md[15:0] (read)
6-42 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications figure 6-27. expansion-card memory or i/ o 16-bit access to 8-bit device timing low byte high byte read data latch read data latch tcdphch tcdclps tcdphch tcdclps tcdcmd tcdchai tcdavcl tcdcmd tcdchai tcdavcl tcdchwdi tcdchwdi tcddvcl tcdchrdi tcddvch tcdchrdi tcddvch tcdchih tcdilcl clk_mem ma<25:1>,npreg,psktsel ma<0> npce<2> npce<1> npiow (or) npior rdnwr niois16 npwait md<7:0> (read) md<7:0> (write)
electrical, mechanical, and thermal specification 6-43 intel? PXA270 processor ac timing specifications 6.5 lcd timing specifications figure 6-28 describes the lcd timing parameters. the lcd pin timing specifications are referenced to the pixel clock (l_pclk_wr). table 6-22 gives the values for the parameters. figure 6-28. lcd timing definitions table 6-22. lcd timing specifications symbol description min max units notes tpclkdv l_pclk_wr rise/fall to l_ldd<17:0> driven valid ? 14 ns 1 tpclklv l_pclk_wr fall to l_lclk_a0 driven valid ? 14 ns 2 tpclkfv l_pclk_wr fall to l_fclk_rd driven valid ? 14 ns 2 tpclkbv l_pclk_wr rise to l_bias driven valid ? 14 ns 2 notes: 1. the lcd data pins can be programmed to be driven on ei ther the rising or falling edge of the pixel clock (l_pclk_wr). 2. these lcd signals can toggle when l_pclk_wr is not clocking (between frames). at this time, they are clocked with the internal version of the pixel cl ock before it is driven out onto the l_pclk_wr pin. l_ldd[17:0] (rise) l_ldd[17:0] (fall) l_pclk_wr l_lclk_a0 l_bias l_fclk_rd t pclkdv t pclklv t pclkfv t pclkbv t pclkdv
6-44 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications 6.6 ssp timing specifications figure 6-29 describes the ssp timing parameters. the ssp pin timing specifications are referenced to sspclk. table 6-23 gives the values for the parameters. note: in figure 6-29 , read the term ?tsfmv? as ?tstxv.? figure 6-30. timing di agram for ssp slave mode transmitting data to an external peripheral figure 6-29. ssp master mode timing definitions table 6-23. ssp master m ode timing specifications symbol description min max units notes ts f m v sspsclk rise to sspsfrm driven valid 21 ns trxds ssprxd valid to sspsclk fall (input setup) 11 ns trxdh sspsclk fall to ssprxd invalid (input hold) 0 ns ts f m v sspsclk rise to ssptxd valid 22 ns sspsclk sspsfrm ssptxd ssprxd t sfmv t sfmv t rxds t rxdh pxa27x processor transmitting data sspsclk (from peripheral) ssptxd (from ssp) pxa27x ssp (slave mode) transmitting data to external peripheral sspsfrm (from peripheral) tsclk2txd_output_delay tsfrm2txd_output_delay pxa27x processor transmitting data sspsclk (from peripheral) ssptxd (from ssp) pxa27x ssp (slave mode) transmitting data to external peripheral sspsfrm (from peripheral) tsclk2txd_output_delay tsfrm2txd_output_delay
electrical, mechanical, and thermal specification 6-45 intel? PXA270 processor ac timing specifications table 6-24. timing specification ssp slave mode transmitting data to external peripheral figure 6-31. timing diagram for ssp slave mode receivi ng data from external peripheral table 6-25. timing specification for ssp slave mode receiving data from external peripheral 6.7 jtag boundary scan timing specifications table 6-26 shows the ac specifications for the jtag boundary-scan test-signals. figure 6-32 shows the timing diagram. parameter description min typ max units tsfrm2txd_output_delay frame to tx data out 10.58 ns tsclk2txd_output_delay clock to tx data out 10.52 ns parameter description min typical max units tsfrm_input_delay frame to rx data capture 5.21 ns tsclk_input_delay clock to rx data capture 5.04 ns trxd_input_delay rx data setup to capture 4.81 ns pxa27 processor receiving data sspsclk (from peripheral) ssprxd (from peripheral) sspsfrm (from peripheral) pxa27x ssp (slave mode receiving data from external peripheral data capture tsclk_input_delay tsfrm_input_delay trxd_input_delay data capture pxa27 processor receiving data sspsclk (from peripheral) ssprxd (from peripheral) sspsfrm (from peripheral) pxa27x ssp (slave mode receiving data from external peripheral data capture tsclk_input_delay tsfrm_input_delay trxd_input_delay data capture table 6-26. boundary scan timing specifications (sheet 1 of 2) symbol parameter min max units notes tbsf tck frequency 0.0 33.33 mhz ? tbsch tck high time 15.0 ? ns measured at 1.5 v tbscl tck low time 15.0 ? ns measured at 1.5 v tbscr tck rise time ? 5.0 ns 0.8 v to 2.0 v tbscf tck fall time ? 5.0 ns 2.0 v to 0.8 v
6-46 electrical, mechanical, and thermal specification intel? PXA270 processor ac timing specifications tbsis1 input setup to tck tdi, tms 4.0 ? ns ? tbsih1 input hold from tck tdi, tms 6.0 ? ns ? tbsis2 input setup to tck ntrst 25.0 ? ns ? tbsih2 input hold from tck ntrst 3.0 ? ns ? tntrst assertion time of ntrst 6 ? ms ? tbsov1 tdo valid delay 1.5 6.9 ns relative to falling edge of tck tof1 tdo float delay 1.1 5.4 ns relative to falling edge of tck figure 6-32. jtag boundary-scan timing table 6-26. boundary scan timing specifications (sheet 2 of 2) symbol parameter min max units notes ca pt u re - ir shift-ir run-test/idle tof1 tbsov1 tbsov1 tbsov1 tbsov1 tbsov1 tbsov1 tbsov1 tbsih1 tbsis1 tbsih1 tbsis1 tbsih2 tbsis2 tbscl tbsch tbsf tck ntrst tms tdi tdo controller state test-logi c -re s et r u n- t e st /id le s e lec t- dr- s c a n se lect - ir- s can exit1 - ir upd a te - ir t e st -l o g i c - res et tntrst
electrical, mechanical, and thermal specification glossary-1 glossary a 3g: an industry term used to describe the next, still-to-c ome generation of wireless ap plications. it represents a move from circuit-switched communications (where a device user has to dial in to a network) to broadband, high-speed, packet-based wireless networks (which are always on). the first generation of wireless communications relied on analog technology, followed by digital wireless communications. the third generation expands the digital capabilities by including high- speed connections and increased reliability. 802.11: wireless specifications developed by the ieee, outlining the means to manage packet traffic over a network and ensure that packets do not collide, which co uld result in the loss of data, when travelling from device to device. 8psk: 8 phase shift key modulation sche me. used in the edge standard. ac ?97 ac-link standard serial in terface for modem and audio ack: handshake packet indicating a positive acknowledgment. active device: a device that is powered and is not in the suspended state. air interface: the rf interface between a mobile cel lular handset and the base station amps: advanced mobile phone se rvice. a term used for analog technolo gies, the first generation of wireless technologies. analog: radio signals that are converted in to a format that allows them to carry data. cellular phones and other wireless devices use analog in geographic ar eas with insufficient digital networks. arm* v5te: an arm* architecture designation indicating th e processor is conforms to arm* architecture version 5, including ?thumb? mode and the ?el segundo? dsp extensions. asynchronous data: data transferred at irregular intervals with relaxed latency requirements. asynchronous ra: the incoming data rate, fs i, and the outgoi ng data rate, fs o, of the ra process are independent (i.e., there is no sh ared master clock). see also rate adaptation . asynchronous src: the incoming sample rate, fsi, and outgoing sample rate, fso, of the src process are independent (i.e., there is no shared master clock). see also sample rate conversion . audio device: a device that sources or sinks sampled analog data. aw g # : the measurement of a wire?s cros s-section, as defined by the american wire gauge standard. babble: unexpected bus activity that persists be yond a specified poin t in a (micro)frame. backlight inverter: a device to drive cold cathode fluorescen t lamps used to illuminate lcd panels. bandwidth: the amount of data transmitted per unit of time, typically bits per second (b/s) or bytes per second (b/s). the size of a network ?pipe? or channel for communications in wired ne tworks. in wireless, it refers to the range of available frequencies that carry a signal. base station :the telephone company?s interface to the mobile station
glossary-2 electrical, mechanical, and thermal specification intel? PXA270 processor glossary bga: ball grid array bfsk: binary frequency shift keying. a coding scheme for digital data. bit: a unit of information used by digital computers. represents the smallest piece of addressable memory within a computer. a bit expresses the choice between two possibilities and is typically represented by a logical one (1) or zero (0). bit stuffing: insertion of a ?0? bit into a data stream to cause an electrical transition on th e data wires, allowing a pll to remain locked. blackberry : a two-way wireless device (pager) made by resear ch in motion (rim) that allows users to check e-mail and voice mail translated into text, as well as pa ge other users of a wireless network service. it has a miniature ?qwerty? keyboard that can be used by your thumbs, and uses sms protocol. a blackberry user must subscribe to the proprietary wireless service that allows for data transmission. bluetooth: a short-range wireless specification that allows for radio connections between devices within a 30-foot range of each other. the name comes from 10th-century danish king harald blata nd (bluetooth), who unified denmark and norway. bpsk : binary phase shift keying. a means of encoding digital data into a signal using phase-modulated communications. b/s: transmission rate expressed in bits per second. b/s: transmission rate expre ssed in bytes per second. btb: branch target buffer bts : base transmitter station buffer: storage used to compensate for a difference in data rates or time of occurrence of events , when transmitting data from one device to another. bulk transfer: one of the four usb transfer ty pes. bulk transfers are non-periodic, large bursty communication typically used for a transfer that can use any available bandwidth and can also be delayed until bandwidth is available. see also transfer type . bus enumeration: detecting and identifying usb devices. byte: a data element that is eight bits in size. capabilities: those attributes of a usb device that are administrated by the host. cas : cycle accurate simulator cas-b4-ras: see cbr. cbr: cas before ras. column address strobe before row address strobe. a fast refresh technique in which the dram keeps track of the next row it needs to refresh, thus simplifying what a system would have to do to refresh the part. cdma: code division multiple access u.s. wireless carri ers sprint pcd and verizon use cdma to allocate bandwidth for users of digital wireless devices. cdma distinguishes between multiple transmissions carried simultaneously on a single wireless signal. it carries the transmissions on that signal, freeing network room for the
electrical, mechanical, and thermal specification glossary-3 intel? PXA270 processor glossary wireless carrier and providing interferen ce-free calls for the user. several versi ons of the standard are still under development. cdma should increase ne twork capacity for wireless carriers an d improve the quality of wireless messaging. cdma is an alternative to gsm. cdpd : cellular digital packet data tel ecommunications companies can use dc pd to transfer data on unused cellular networks to other users. if one section, or ?cell? of the network is overtaxed, dcpd automatically allows for the reallocation of services. cellular: technology that senses analog or digital transmissions from transmitters that have areas of coverage called cells. as a user of a cellular phone moves between transmitters from one cell to another, the users? call travels from transmitter to transmitter uninterrupted. circuit switched : used by wireless carriers, this method lets a user connect to a network or the internet by dialing in, such as with a traditional phone line. circuit switche d connections are typically slower and less reliable than packet-switched networks, but are curr ently the primary method of network access for wireless users in the u.s. cf : compact flash memory and i/o card interface characteristics: those qualities of a usb device that are unchang eable; for example, the device class is a device characteristic. client: software resident on the host that in teracts with the usb system software to arrange data transfer between a function and the host. the client is often the da ta provider and consumer for transferred data. cml: current mode logic configuring software: software resident on the host software that is responsible for configuring a usb device. this may be a system configuration or software specific to the device. control endpoint : a pair of device endpoints with the same endpoint number that are used by a control pipe. control endpoints transfer data in both directions and, therefore, use both endpoint directions of a device address and endpoint number combination. thus, each co ntrol endpoint consumes two endpoint addresses. control pipe: same as a message pipe. control transfer: one of the four usb transfer types. control transfers support configuration/command/status type communications between client and function. see also transfer type . crc: see cyclic redundancy check. csp: chip scale package. cte: coefficient of thermal expansion cti: computer telephony integration. cyclic redundancy check (crc): a check performed on data to see if an error has occurr ed in transmitting, reading, or writing the data. the result of a crc is typically stored or transmitt ed with the checked data. the stored or transmitted result is compared to a crc calculated for the data to determine if an error has occurred. d-cache : data cache dect : the digital european cordle ss telecommunications standard default address: an address defined by the usb specification and us ed by a usb device when it is first powered or reset. the default address is 00h.
glossary-4 electrical, mechanical, and thermal specification intel? PXA270 processor glossary default pipe: the message pipe created by the usb system so ftware to pass control and status information between the host and a usb device?s endpoint zero. device: a logical or physical entity that performs a function. the actual entity described depends on the context of the reference. at the lowest level, ?device? may refer to a single hardware component, as in a memory device. at a higher level, it may refer to a collection of hardware com ponents that perform a particul ar function, su ch as a usb interface device. at an even higher level, device may refer to the functi on performed by an entity attached to the usb; for example, a data/fax modem device. devices may be physical, elect rical, addressable, and logical. when used as a non-specific reference, a us b device is either a hub or a function. device address: a seven-bit value representing the address of a device on the usb. the device address is the default address (00h) when the usb devi ce is first powered or the device is re set. devices are assigned a unique device address by the usb system software. device endpoint: a uniquely addressable portion of a usb device th at is the source or sink of information in a communication flow between th e host and device. see also endpoint address . device resources: resources provided by usb devices, such as buffer space and endpoints. see also host resources and universal serial bus resources . device software: software that is responsible for using a usb device. this software may or may not also be responsible for configur ing the device for use. dma : direct memory access downstream: the direction of data flow from the host or aw ay from the host. a downstream port is the port on a hub electrically farthest from the ho st that generates downstream data tr affic from the hub. downstream ports receive upstream data traffic. dqpsk : differential quadrature phase shift keying a modulation technique used in tdma. driver: when referring to hardware, an i/o pa d that drives an external load. wh en referring to software, a program responsible for interfacing to a hardwa re device, that is, a device driver. dsp : digital signal processing dstn passive lcd panel. dual band mobile phone: a phone that supports both analog and digital technologies by picking up analog signals when digital signals fade. most mobile phones are not dual-band. dword: double word. a data element that is two words (i.e., four bytes or 32 bits) in size. dynamic insertion and removal: the ability to attach and remove devices while the host is in operation. e2prom : see electrically erasable prog rammable read only memory. eav: end of active video edge: enhanced data gsm environment. a faster version of the gsm standard. it is faster because it can carry messages using broadband networks that employ more bandwidth than standard gsm networks. eeprom: see electrically erasable prog rammable read only memory. electrically erasable programmabl e read only memory (eeprom): non-volatile re-writable memory storage technology.
electrical, mechanical, and thermal specification glossary-5 intel? PXA270 processor glossary end user: the user of a host. endpoint: see device endpoint. endpoint address: the combination of an endpoint number and an endpoint direction on a usb device. each endpoint address supports data transfer in one direction. endpoint direction: the direction of data transfer on the usb. the direction can be eith er in or out. in refers to transfers to the host; out refers to transfers from the host. endpoint number: a four-bit value between 0h and fh, inclusive, associated with an endpoint on a usb device. envelope detector: an electronic circuit inside a us b device that monitors the usb data lines and detects certain voltage related signal characteristics. eof: end-of-(micro)frame. eop: end-of-packet. eotd: enhanced observed time difference etm : embedded trace macrocell, th e arm* real-time trace capability external port: see port. eye pattern: a representation of usb signaling that provides mi nimum and maximum voltage levels as well as signal jitter. far : fault address register, part of the arm* architecture. false eop: a spurious, usually nois e-induced event that is interpreted by a packet receiver as an eop. fdd : the mobile station transmits on one frequency; the base station transmits on another frequency fdm: frequency division multiplexing. each mobile station transmits on a different frequency (within a cell). fdma: frequency division multiple access. an analog standa rd that lets multiple users access a group of radio frequency bands and eliminates interference of message traffic. fhss : see frequency hoppin g spread spectrum. fiq : fast interrupt request. see interrupt request. frame: a 1 millisecond time base established on full-/low-speed buses. frame pattern: a sequence of frames that exhibi t a repeating pattern in the number of samples transmitted per frame. for a 44.1 khz audio transfer, th e frame pattern could be nine frames containing 44 samples followed by one frame containing 45 samples. frequency hopping spread spectrum : a method by which a carrier spreads out packets of information (voice or data) over different frequencies. for example, a phone call is carried on several different frequencies so that when one frequency is lost another picks up the call without breaking the connection. fs: see sample rate. fsr : fault status register, part of the arm* architecture.
glossary-6 electrical, mechanical, and thermal specification intel? PXA270 processor glossary full-duplex: computer data transmission occurring in both directions simultaneously. full-speed: usb operation at 12 mb/s. see also low-speed and high-speed . function: a usb device that provides a capability to the host, such as an isdn connection, a digital microphone, or speakers. gmsk: gaussian minimum shift keying. a modulation scheme used in gsm. gprs: general packet radio service a technology that sends packets of data across a wireless network at speeds up to 114 kbps. unlike circuit-switched networks, wireless users do not have to dial in to networks to download information; gprs wireless devices are ?always on? in that they can send a nd receive data without dial-ins. gprs works with gsm. gps: global positioning systems gsm: global system for mobile communications. a standa rd for how data is coded and transferred through the wireless spectrum. the european wireless standard, also us ed in parts of asia, gsm is an alternative to cdma. gsm digitizes and compresses data and se nds it across a channel with two other streams of user data. gsm is based on tdma technology. hamming distance: the distance (number of bits) between encoded values that can change without causing a decode into the wrong value. handshake packet: a packet that acknowledges or rejects a specific condition. for examples, see ack and nak. hdml: handheld device markup language. hdml uses hypert ext transfer protocol (http) to display text versions of web pages on wireless devices. unlike wm l, hdml is not based on xml. hdml does not allow scripts, while wml uses a variant of javascript. web site developers using hdml must re-code their web pages in hdml to be viewed on the smaller screen sizes of handheld devices. harp: windows ce standard development platform spec (hardware adaptati on reference platform) high-bandwidth endpoint: a high-speed device endpoint that transfers more than 1024 bytes and less than 3073 bytes per microframe. high-speed: usb operation at 480 mb/s. see also low-speed and full-speed . host : the host computer system where the usb host controller is installed. this includes the host hardware platform (cpu, bus, and so forth.) and the operating system in use. host controller: the host?s usb interface. host controller driver (hcd): the usb software layer that abstracts the host controller hardware. the host controller driver provides an spi for interaction with a host controller. the host controller driver hides the specifics of the host contro ller hardware implementation. host resources: resources provided by the host, such as buffer space and interrupts. see also device resources and universal serial bus resources . hstl: high-speed transceiver logic hub: a usb device that provides addi tional connections to the usb. hub tier: one plus the number of usb links in a communication path between the host and a function.
electrical, mechanical, and thermal specification glossary-7 intel? PXA270 processor glossary immu: instruction memory management unit, part of the intel xscale? core. i-mode: a japanese wireless service for transferring pack et-based data to handheld devices created by ntt docomo. i-mode is based on a compact versio n of html and does not currently use wap. i-cache: instruction cache ibis: i/o buffer information specification is a behavioral descript ion of the i/o buffers and package characteristics of a semiconductor device. ibis models use a standard format to make it easier to import data into circuit simulation software packages. iden: integrated digital enhanced network. a technology that allows users to access phone calls, two-way radio transmissions, paging and data transmissions from one wireless device. iden was developed by motorola and based on tdma. interrupt request (irq): a hardware signal that allows a device to request attention from a host. the host typically invokes an interrupt service routine to handle the condition that caused the request. interrupt transfer: one of the four usb transfer types. interr upt transfer character istics are small data, non-periodic, low-frequency, and bounded-latency. interrupt transfers are typically used to handle service needs. see also transfer type . i/o request packet: an identifiable request by a software client to move data between itself (on the host) and an endpoint of a device in an appropriate direction. irda: infrared development association irp: see i/o request packet. irq: see interrupt request. isi: inter-signal interference. data ghosting caused when mu lti-path delay causes previous symbols to interfere with the one curren tly being processed. ism: industrial, scientific, and medical ba nd. part of the wireless spectrum that is less regulated, such as 802.11. isochronous data: a stream of data whose timing is implied by its delivery rate. isochronous device: an entity with isochronous endpoints, as defined in the usb specification, that sources or sinks sampled analog streams or synchronous data streams. isochronous sink endpoint : an endpoint that is capable of consuming an isochronous data stream that is sent by the host. isochronous source endpoint: an endpoint that is capable of producing an isochronous data stream and sending it to the host. isochronous transfer: one of the four usb transfer types. isochr onous transfers are used when working with isochronous data. isochronous transfers provide periodic, continuous communication between host and device. see also transfer type . jitter: a tendency toward lack of synchronization caused by m echanical or electrical ch anges. more specifically, the phase shift of digital pulses over a transmission medium. kb/s: transmission rate expressed in kilobits per s econd. a measurement of bandwidth in the u.s.
glossary-8 electrical, mechanical, and thermal specification intel? PXA270 processor glossary kb/s: transmission rate expressed in kilobytes per second. little endian: method of storing data that places the least significant byte of multiple-byte values at lower storage addresses. for example, a 16-bit integer stored in little endian format places the least significant byte at the lower address and the most significan t byte at the next address. loa: loss of bus activity characterized by an sop without a corresponding eop. low-speed: usb operation at 1.5 mb/s. see also full-speed and high-speed . lsb: least significant bit. lsb: least significant byte. lvds: low-voltage differential signal mac : multiply accumulate unit mb/s: transmission rate expressed in megabits per second. mb/s: transmission rate expressed in megabytes per second. mc: media center. a combination digital set-top box, video and music jukebox, personal video recorder and an internet gateway and firewall that hooks up to a broadband connection. message pipe: a bidirectional pipe that transfers data using a request/data/status paradigm. the data has an imposed structure that allows requests to be reliably identified and communicated. microframe: a 125 microsecond time base established on high-speed buses. mmc: multimedia card - small form factor memory and i/o card mmx technology : the intel? mmx? technology comp rises a set of instructions th at are designed to greatly enhance the performance of advanced media and comm unications applications. see chapter 10 of the intel? architecture software developers manual, volume 3: system programming guid e, order #245472. mobile station: cellular telephone handset m-psk: multilevel phase shift keying. a convention for encoding digital data in which there are multiple states. mmu: memory management unit, part of the intel xscale? core. msb: most significant bit. msb: most significant byte. msl: mobile scalable link. nak: handshake packet indicating a negative acknowledgment. non return to zero invert (nrzi): a method of encoding serial data in which ones and zeroes are represented by opposite and alternating high and low voltages where there is no return to zero (reference) voltage between encoded bits. eliminates the need for clock pulses. nrzi: see non return to zero invert. object: host software or data struct ure representing a usb entity.
electrical, mechanical, and thermal specification glossary-9 intel? PXA270 processor glossary ofdm : see orthogonal frequency division multiplexing. orthogonal frequency division multiplexing: a special form of multi-carrier modulation. in a multi-path channel, most conventional modulation techniques are sensitive to inter-sy mbol interference unless the channel symbol rate is small compared to the delay spread of the channel. of dm is significantly less sensitive to inter-symbol interference, because a sp ecial set of signals is us ed to build the composit e transmitted signal. the basic idea is that each bit occupies a frequency-time windo w that ensures little or no di stortion of the waveform. in practice, it means that bits are transmitted in parall el over a number of frequency-nonselective channels. packet: a bundle of data organized in a group for transmission. packets typically contain three elements: control information (for example, source, destination, and length ), the data to be transfer red, and error detection and correction bits. packet data is the basi s for packet-switched networks, which eliminate the need to dial-in to send or receive information, becau se they are ?always on.? packet buffer: the logical buffer used by a usb device for sending or receiving a single packet. this determines the maximum packet size the device can send or receive. packet id (pid): a field in a usb packet that indicates the type of packet, a nd by inference, the format of the packet and the type of error de tection applied to the packet. packet switched network: networks that transfer packets of data. pcmcia : personal computer memory card interface association (pc card) pcs: personal communications services. an alternative to cellular, pcd work s like cellular technology because it sends calls from transmitter to transmitt er as a caller moves. but pcs uses it s own network, not a cellular network, and offers fewer ?blind spots? than cellular, where calls are not available. pcs transm itters are generally closer together than their cellular counterparts. pda : personal digital assistant. a mobi le handheld device that gives users acces s to text-based in formation. users can synchronize their pdas with a pc or network; so me models support wireless communication to retrieve and send e-mail and get information from the internet. phase: a token, data, or handshake packet. a transaction has three phases. phase locked loop (pll): a circuit that acts as a phase detector to keep an osci llator in phase with an incoming frequency. physical device: a device that has a physical implementation; for example, speakers, microphones, and cd players. pid: see packet id or process id. pio : programmed input/output pipe: a logical abstraction representing the association between an endpoint on a device and software on the host. a pipe has several attributes; for example, a pipe may tran sfer data as streams (stream pipe) or messages (message pipe). see also stream pipe and message pipe . pll: see phase locked loop. pm : phase modulation. polling: asking multiple devices, one at a time, if they have any data to transmit. por: see power on reset.
glossary-10 electrical, mechanical, and thermal specification intel? PXA270 processor glossary port: point of access to or from a system or circuit. for the usb, the poi nt where a usb device is attached. power on reset (por): restoring a storage device, regi ster, or memory to a predet ermined state when power is applied. process id : process identifier programmable data rate: either a fixed data rate (sin gle-frequency endpoints), a li mited number of data rates (32 khz, 44.1 khz, 48 khz, ?), or a continuously progr ammable data rate. the exact programming capabilities of an endpoint must be reported in the appropriate class-specific endpoint descriptors. protocol: a specific set of rules, procedures, or conventions relating to format and timing of data transmission between two devices. psp: programmable serial protocol pwm: pulse width modulator qbs: qualification by similarity. a technique allowed by je dec for part qualification wh en target parameters are fully understood and data exist to warrant omitting a specific test. qam: quadrature amplitude modulation. a coding scheme for digital data. qpsk: quadrature phase shift keying. a convention for encodi ng digital data into a signal using phase-modulated communications. ra: see rate adaptation. radio frequency device: these devices use radio frequencies to tran smit data. one typical use is for bar code scanning of products in a warehouse or distribution cent er, and sending that information to an erp database. rate adaptation: the process by which an incoming da ta stream, sampled at fs i, is converted to an outgoing data stream, sampled at fs o, with a certain loss of quality, determined by the rate adaptation algorithm. error control mechanisms are required for the process. fs i and fs o can be different and asynchronous. fs i is the input data rate of the ra; fs o is the output data rate of the ra. request: a request made to a usb device contained within the data portion of a setup packet. retire: the action of completing service fo r a transfer and notifying the appr opriate software client of the completion. rgbt: red, green, blue, transparency rom: read only memory. root hub: a usb hub directly attach ed to the host controller. this hub (tier 1) is attached to the host. root port: the downstream port on a root hub. rtc: real-time clock sa-1110: strongarm * based applications processor for handheld products intel? strongarm* sa-1111: companion chip for the intel? sa-1110 processor sad: sum of absolute differences
electrical, mechanical, and thermal specification glossary-11 intel? PXA270 processor glossary sample: the smallest unit of data on which an endpoint operates; a property of an endpoint. sample rate (fs): the number of samples per sec ond, expressed in hertz (hz). sample rate conversion (src): a dedicated implementation of the ra process for use on sampled analog data streams. the error control mechanism is replaced by interpolating techniqu es. service a procedure provided by a system programming interface (spi). satellite phone: phones that connect callers by satellite. users have a world-wide alternative to terrestrial connections. typical use is for isolated users, such as cr ews of deep-see oil rigs with phones configured to connect to a satellite service. sav: start of active video saw: surface acoustic wave filter sdram: synchronous dynamic random access memory. service interval: the period between consecutiv e requests to a usb endpoint to send or receive data. service jitter: the deviation of service delivery from its scheduled delivery time. service rate: the number of services to a given endpoint per unit time. simd: single instruction multiple data (a parallel processi ng architecture). smart phone: a combination of a mobile phone and a pda, which allow users to communicate as well as perform tasks; such as, accessing the internet and storing contacts in a database. smart phones have a pda-like screen. smrom: synchronous mask rom sms: short messaging service. a service through which user s can send text-based messages from one device to another. the message can be up to 160 characters and ap pears on the screen of the receiving device. sms works with gsm networks. soc: system on chip sof: see start-of-frame. sop: start-of-packet. spi: see system program ming interface. also, ?serial pe ripheral interface protocol. spi: serial peripheral interface split transaction: a transaction type supported by host controllers and hubs. this transaction type allows full- and low-speed devices to be attached to hubs operating at high-speed. spread spectrum: an encoding technique patented by actress he dy lamarr and composer george antheil, which broadcasts a signal over a range of frequencies. sram: static random access memory. src: see sample rate conversion. sse: streaming simd extensions
glossary-12 electrical, mechanical, and thermal specification intel? PXA270 processor glossary sse2: streaming simd extensions 2: for intel architectur e machines, 144 new instru ctions, a 128-bit simd integer arithmetic and 128-bit simd double precision floating point instructions, enabling enhanced multimedia experiences. ssp: synchronous serial port sstl: stub series terminated logic stage: one part of the sequence composing a control transfer; stages include the setup stage, the data stage, and the status stage. start-of-frame (sof): the first transaction in each (micro)frame. an sof allows endp oints to identify the start of the (micro)frame and synchronize inte rnal endpoint cloc ks to the host. stream pipe: a pipe that transfers data as a stream of samples with no defined usb structure swi: software interrupt. synchronization type: a classification that characteri zes an isochronous endpoint?s capability to connect to other isochronous endpoints. synchronous ra: the incoming data rate, fsi, and the outgoing data rate, fso, of the ra process are derived from the same master clock. there is a fixed relation between fsi and fso. synchronous src: the incoming sample rate, fsi, and outgoing sample rate, fso, of the src process are derived from the same master clock. there is a fixed relation between fsi and fso. system programming interface (spi): a defined interface to services provided by system software. tc: temperature cycling tdd: time division duplexing the mobile station and the base station transmit on same frequency at different times. tdm: see time division multiplexing. tdma: time division multiple access. td ma protocol allows multiple users to access a single radio frequency by allocating time slots for use to multiple voice or data calls. tdma breaks down data transmissions, such as a phone conversation, into fragments and transmits each frag ment in a short burst, assigning each fragment a time slot. with a cell phone, the caller would not detect this fragmentation. tdma works with gsm and digital cellular services. tdr: see time domain reflectometer. termination: passive components attached at the end of cables to prevent signals from being reflected or echoed. tft: thin film twist, a type of active lcd panel. three-state: a high-impedance state in which th e output is floating and is electrically isolated from the buffer's circuitry. time division multiplexing (tdm): a method of transmitting multiple signals (data, voice, and/or video) simultaneously over one communications medium by inte rleaving a piece of each signal one after another. time domain reflectometer (tdr): an instrument capable of measuring impedance ch aracteristics of the usb signal lines.
electrical, mechanical, and thermal specification glossary-13 intel? PXA270 processor glossary time-out: the detection of a lack of bus activ ity for some predet ermined interval. token packet: a type of packet that iden tifies what transaction is to be performed on the bus. tpv: third party vendor transaction: the delivery of service to an endpoint; consists of a token packet, optional data packet, and optional handshake packet. specific packets are allowe d/required based on the transaction type. transaction translator: a functional component of a usb hub. the transaction translator responds to special high-speed transactions and translates them to full/low-sp eed transactions with full/low-speed devices attached on downstream facing ports. transfer: one or more bus transactions to move information between a software client and its function. transfer type: determines the characteristics of the data flow between a software client and its function. four standard transfer types are defined: control, interrupt, bulk, and isochronous. ts: thermal shock turn-around time: the time a device needs to wait to begin transmi tting a packet after a packet has been received to prevent collisions on the usb. this time is based on the length and propagation delay characteristics of the cable and the location of the transmitting device in relation to other devices on the usb. uart: universal asynchronous recei ver/transmitter serial port universal serial bus driver (usbd): the host resident software entity responsible for providing common services to clients that are manipulating one or more functions on one or more host controllers. universal serial bus resources: resources provided by the usb, such as bandwidth and power. see also device resources and host resources . upstream: the direction of data flow towards the host. an upst ream port is the port on a de vice electrically closest to the host that generates up stream data traffic from the hub. upstream ports recei ve downstream data traffic. usbd: see universal serial bus driver . usb-if: usb implementers forum, inc. is a nonprofit corporation formed to facilitate the development of usb compliant products and pr omote the technology. vbi: vertical blanking interval, al so known as the ?backporch?. virtual device: a device that is represented by a software interface layer. an example of a virtual device is a hard disk with its associated device driver and client softwa re that makes it able to reproduce an audio.wav file. vlio: variable latency input/output interface. yuv: a method of characterizing video signals typically used in digital cameras and pal television specifying luminance and chrominance. wa p : wireless application protocol. wap is a set of protocol s that lets users of mobile phones and other digital wireless devices access internet cont ent, check voice mail and e-mail, r eceive text of faxes and conduct transactions. wap works with multiple standards, including cdma and gsm. not all mobile devices support wa p.
glossary-14 electrical, mechanical, and thermal specification intel? PXA270 processor glossary w-cdma: wideband cdma, a third generation wireless technology under development that allows for high-speed, high-quality data transmission. derived from cdma, w-cdma digitizes and transmits wireless data over a broad range of frequencies. it requires more bandwid th than cdma, but offers fa ster transmission because it optimizes the use of multiple wireless si gnals, instead of one, as does cdma. wireless lan: a wireless lan uses radio frequency technology to transmit network messages through the air for relatively short distances, like acros s an office building or a college cam pus. a wireless lan can serve as a replacement for, or an extensi on to, a traditional wired lan. wireless spectrum: a band of frequencies where wireless signals travel carrying voice and data information. word: a data element that is fo ur bytes (32 bits) in size. wml: wireless markup language, a version of hdml is based on xml. wireless applications developers use wml to re-target content for wireless devices.
intel? PXA270 processor emts index-1 index a about this document ..... ........... ........... ........... ........... .......1 ac timing specifications ..................................................1 ac test load specifications ......................................1 gpio timing specifications ....................................11 jtag boundary scan timing sp ecifications ..........45 lcd timing specifications .....................................43 memory and expansion-card timing specifications 12 flash memory parameters and timing diagrams 23 sram parameters and timing diagrams ........33 variable-latency i/o parameters and timing dia- grams ................................................36 reset and power manager ti ming specifications .....2 deep-sleep mode timing ..................................7 frequency-change timing ...............................10 gpio reset timing ............................................5 hardware reset timing .....................................4 idle-mode timing ............................................10 sleep mode timing ............................................6 standby-mode timing .....................................10 voltage-change timing ...................................11 watchdog reset timing .......... ........... ......... .......5 ssp timing specifications .......................................44 applicable documents .......................................................2 e electrical specifications .....................................................1 absolute maximum ratings .......................................1 clk_pio and clk_tout specifications .............12 dc specification ........................................................8 operating conditions .................................................1 oscillator electrical specifications ............................9 oscillator electrical specs 13.000-mhz oscillator specif ications .. ...........11 32.768-khz oscillator specif ications ..... ...........9 power-consumption specifications ...........................6 expansion-card interface para meters and timing diagrams 40 f flash memory read paramete rs and timing diagrams ..23 flash memory write parameters and timing diagrams .30 functional overview ..........................................................1 g gpio states in deep-sleep mode ....................................... 9 i internal sram read/write timing specifications ......... 12 introduction ........... ........... ........... ........... ........... ......... ........ 1 about this document ................................................ 1 applicable documents ............................................... 2 number representation ............................................. 1 typographical conventi ons ........... ........... ......... ........ 1 j junction to case temperature thermal resistance .......... 7 n number representation ..................................................... 1 p package information .......................................................... 1 pinlist ................................................................................. 1 power-on timing specifications ....................................... 2 processor markings ............................................................ 7 processor materials ............................................................ 6 r rom parameters and timing diagrams .......................... 18 s sdram parameters and timing diagrams .................... 12 sram read parameters and timing diagrams .............. 33 sram write parameters and timing diagrams ............. 33 t tray drawing ..................................................................... 8 typographical conventions ............ ......... ......... ......... ........ 1 v variable latency i/o read timing .................................. 37 variable-latency i/o write timing ................................ 38
index-2 intel? PXA270 processor emts index

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